Hi,
On Wed, Apr 1, 2020 at 1:14 AM Maulik Shah <mkshah@xxxxxxxxxxxxxx> wrote:
>
> > + * - The first TCS block is special in that it has registers to control
> > + * interrupts (RSC_DRV_IRQ_XXX). Space for these registers is reserved
> > + * in all TCS blocks to make the math easier, but only the first one
> > + * matters.
>
> First TCS block is not special, the RSC_DRV_IRQ_XXX registers are common
> for all
Ah. I think I see it now. It's much easier to talk about this with
my old struct definition. Right now I have it documented as:
/* 0x2a0 = 672 bytes big (see RSC_DRV_TCS_OFFSET) */
struct tcs_hw {
u32 irq_enable;
u32 irq_status;
u32 irq_clear;
char opaque_00c[0x4];
u32 cmd_wait_for_cmpl;
u32 control;
u32 status;
u32 cmd_enable;
char opaque_020[0x10];
struct tcs_cmd_hw tcs_cmd_hw[MAX_CMDS_PER_TCS];
char opaque_170[0x130];
};
...but you're saying that it's actually:
/* 0x2a0 = 672 bytes big (see RSC_DRV_TCS_OFFSET) */
struct tcs_hw {
u32 cmd_wait_for_cmpl;
u32 control;
u32 status;
u32 cmd_enable;
char opaque_010[0x10];
struct tcs_cmd_hw tcs_cmd_hw[MAX_CMDS_PER_TCS];
char opaque_160[0x140];
};
So it's still 672 bytes big but the extra "opaque" at the end is where
those bytes go. Then, before the first TCS, there's actually 0x10
bytes of IRQ stuff. OK, I will adjust the diagrams.
-Doug
