Hi, On Wed, Dec 4, 2019 at 8:43 PM Sandeep Maheswaram <sanm@xxxxxxxxxxxxxx> wrote: > > diff --git a/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.yaml Hrm. Probably should have given this same comment on the USB3 yaml bindings too, but I think the file name should be: qcom,qusb2-phy.yaml Specifically I think that's what Rob H has been requesting elsewhere. > new file mode 100644 > index 0000000..3ef94bc > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.yaml > @@ -0,0 +1,129 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > + > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/phy/qcom-qusb2-phy.yaml#"; If you change the name to add the comma (as per above), don't forget to update your ID. > +$schema: "http://devicetree.org/meta-schemas/core.yaml#"; > + > +title: Qualcomm QUSB2 phy controller > + > +maintainers: > + - Manu Gautam <mgautam@xxxxxxxxxxxxxx> > + > +description: | nit: don't need the "|" unless carriage returns are important. > + QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets. > + > +properties: > + compatible: > + enum: > + - qcom,msm8996-qusb2-phy > + - qcom,msm8998-qusb2-phy > + - qcom,sdm845-qusb2-phy > + > + reg: > + description: > + offset and length of the PHY register set. No description, just maxItems: 1 I think. This seemed to be what Rob H suggested in USB3 bindings with regards to resets where the description was just generic [1]. > + "#phy-cells": > + const: 0 > + > + clocks: > + maxItems: 3 > + description: > + a list of phandles and clock-specifier pairs, > + one for each entry in clock-names. > + > + clock-names: > + items: > + - const: cfg_ahb #phy config clock > + - const: ref #19.2 MHz ref clk > + - const: iface #phy interface clock (Optional) Please take the same type of feedback you got for the USB3 bindings with regards to clocks / clock-names. > + vdda-pll-supply: > + description: > + Phandle to 1.8V regulator supply to PHY refclk pll block. > + > + vdda-phy-dpdm-supply: > + description: > + Phandle to 3.1V regulator supply to Dp/Dm port signals. > + > + resets: > + description: > + Phandle to reset to phy block. No description, just maxItems: 1 I think [1]. > + nvmem-cells: > + description: > + Phandle to nvmem cell that contains 'HS Tx trim' > + tuning parameter value for qusb2 phy. Add maxItems: 1 ? > + qcom,tcsr-syscon: > + description: > + Phandle to TCSR syscon register region. > + $ref: /schemas/types.yaml#/definitions/cell > + > + qcom,imp-res-offset-value: > + description: > + It is a 6 bit value that specifies offset to be > + added to PHY refgen RESCODE via IMP_CTRL1 register. It is a PHY > + tuning parameter that may vary for different boards of same SOC. > + This property is applicable to only QUSB2 v2 PHY (sdm845). > + $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 63 ...and, I think: default: 0 > + qcom,hstx-trim-value: > + description: > + It is a 4 bit value that specifies tuning for HSTX > + output current. > + Possible range is - 15mA to 24mA (stepsize of 600 uA). > + See dt-bindings/phy/phy-qcom-qusb2.h for applicable values. > + This property is applicable to only QUSB2 v2 PHY (sdm845). > + Default value is 22.2mA for sdm845. > + $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 15 default: 3 > + qcom,preemphasis-level: > + description: > + It is a 2 bit value that specifies pre-emphasis level. > + Possible range is 0 to 15% (stepsize of 5%). > + See dt-bindings/phy/phy-qcom-qusb2.h for applicable values. > + This property is applicable to only QUSB2 v2 PHY (sdm845). > + Default value is 10% for sdm845. > + $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 3 default: 2 > + qcom,preemphasis-width: > + description: > + It is a 1 bit value that specifies how long the HSTX > + pre-emphasis (specified using qcom,preemphasis-level) must be in > + effect. Duration could be half-bit of full-bit. > + See dt-bindings/phy/phy-qcom-qusb2.h for applicable values. > + This property is applicable to only QUSB2 v2 PHY (sdm845). > + Default value is full-bit width for sdm845. > + $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 1 default: 0 > +required: > + - compatible > + - reg > + - "#phy-cells" > + - clocks > + - clock-names > + - vdda-pll-supply > + - vdda-phy-dpdm-supply > + - resets > + > + > +examples: > + - | #include <dt-bindings/clock/qcom,gcc-msm8996.h> > + hsusb_phy: phy@7411000 { > + compatible = "qcom,msm8996-qusb2-phy"; > + reg = <0x7411000 0x180>; > + #phy-cells = <0>; > + > + clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, > + <&gcc GCC_RX1_USB2_CLKREF_CLK>, The comma at the end is a syntax error. make dt_binding_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/phy/qcom-qusb2-phy.yaml [1] https://lore.kernel.org/r/20191213212313.GA21092@bogus -Doug
