Re: [PATCH 2/5] clk: qcom: apcs-msm8916: get parent clock names from DT

[Stephen Boyd <sboyd@xxxxxxxxxx>]

Quoting Jorge Ramirez-Ortiz (2019-08-26 09:45:07)
> @@ -76,10 +88,11 @@ static int qcom_apcs_msm8916_clk_probe(struct platform_device *pdev)
>         a53cc->src_shift = 8;
>         a53cc->parent_map = gpll0_a53cc_map;
>  
> -       a53cc->pclk = devm_clk_get(parent, NULL);
> +       a53cc->pclk = of_clk_get(parent->of_node, pll_index);

Presumably the PLL was always index 0, so why are we changing it to
index 1 sometimes? Seems unnecessary.