On 16-06-19, 21:37, Bjorn Andersson wrote: > On Wed 12 Jun 02:17 PDT 2019, Vinod Koul wrote: > > > We have couple of instances in the driver with unnecessary > > u64 casts, drop them. > > > > Signed-off-by: Vinod Koul <vkoul@xxxxxxxxxx> > > --- > > drivers/clk/qcom/clk-alpha-pll.c | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c > > index 0ced4a5a9a17..b48707693ffd 100644 > > --- a/drivers/clk/qcom/clk-alpha-pll.c > > +++ b/drivers/clk/qcom/clk-alpha-pll.c > > @@ -832,7 +832,7 @@ static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, > > int div; > > > > /* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */ > > - div = DIV_ROUND_UP_ULL((u64)parent_rate, rate) - 1; > > + div = DIV_ROUND_UP_ULL(parent_rate, rate) - 1; > > Afaict DIV_ROUND_UP_ULL() will first add "parent_rate" and "rate" and > then stash this in a unsigned long long and do the division. So what > happens if parent_rate + rate > 32 bits on a 32-bit target? > > (Shouldn't there be a cast of (ll) in the macro to ULL?) Agreed, though DIV_ROUND_DOWN_ULL does it correctly, right fix would be to make it: #define DIV_ROUND_UP_ULL(ll, d) DIV_ROUND_DOWN_ULL(unsigned long long(ll) + (d) - 1, (d)) I will post that as well.. Thanks -- ~Vinod
