Hi Stephen, On Thu, Jun 6, 2019 at 2:27 AM Stephen Boyd <swboyd@xxxxxxxxxxxx> wrote: > > Quoting Vivek Gautam (2019-06-04 21:55:26) > > On Wed, Jun 5, 2019 at 4:16 AM Stephen Boyd <swboyd@xxxxxxxxxxxx> wrote: > > > > > > Quoting Bjorn Andersson (2019-06-04 15:37:00) > > > > On Tue 04 Jun 15:29 PDT 2019, Stephen Boyd wrote: > > > > > > > > > The SMMU that sits in front of the QUP needs to be programmed properly > > > > > so that the i2c geni driver can allocate DMA descriptors. Failure to do > > > > > this leads to faults when using devices such as an i2c touchscreen where > > > > > the transaction is larger than 32 bytes and we use a DMA buffer. > > > > > > > > > > > > > I'm pretty sure I've run into this problem, but before we marked the > > > > smmu bypass_disable and as such didn't get the fault, thanks. > > > > > > > > > arm-smmu 15000000.iommu: Unexpected global fault, this could be serious > > > > > arm-smmu 15000000.iommu: GFSR 0x00000002, GFSYNR0 0x00000002, GFSYNR1 0x000006c0, GFSYNR2 0x00000000 > > > > > > > > > > Add the right SID and mask so this works. > > > > > > > > > > Cc: Sibi Sankar <sibis@xxxxxxxxxxxxxx> > > > > > Signed-off-by: Stephen Boyd <swboyd@xxxxxxxxxxxx> > > > > > --- > > > > > arch/arm64/boot/dts/qcom/sdm845.dtsi | 1 + > > > > > 1 file changed, 1 insertion(+) > > > > > > > > > > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi > > > > > index fcb93300ca62..2e57e861e17c 100644 > > > > > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi > > > > > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi > > > > > @@ -900,6 +900,7 @@ > > > > > #address-cells = <2>; > > > > > #size-cells = <2>; > > > > > ranges; > > > > > + iommus = <&apps_smmu 0x6c0 0x3>; > > > > > > > > According to the docs this stream belongs to TZ, the HLOS stream should > > > > be 0x6c3. > > > > > > Aye, I saw this line in the downstream kernel but it doesn't work for > > > me. If I specify <&apps_smmu 0x6c3 0x0> it still blows up. I wonder if > > > my firmware perhaps is missing some initialization here to make the QUP > > > operate in HLOS mode? Otherwise, I thought that the 0x3 at the end was > > > the mask and so it should be split off to the second cell in the DT > > > specifier but that seemed a little weird. > > > > Two things here - > > 0x6c0 - TZ SID. Do you see above fault on MTP sdm845 devices? > > No. I see the above fault on Cheza. Right, expected. > > > 0x6c3/0x6c6 - HLOS SIDs. My bad, the other SID is 0x6D6. > > Why are there two? I see some mentions of GSI mode near these SIDs so > maybe GSI has to be used for DMA here to get the above two SIDs at the > IOMMU? Otherwise if we do the non-GSI mode of DMA we're going to use the > "TZ" SID? Yea, one for GSI, and the other one for non-GSI DMA. I am unsure at this point about the use of TZ SID, but i would assume this is the SID that's used by the qup firmware, and therefore on MTP TZ programs this SID. > > > > > Cheza will throw faults for anything that is programmed with TZ on mtp > > as all of that should be handled in HLOS. The firmwares of all these > > peripherals assume that the SID reservation is done (whether in TZ or HLOS). > > > > I am inclined to moving the iommus property for all 'TZ' to board dts files. > > MTP wouldn't need those SIDs. So, the SOC level dtsi will have just the > > HLOS SIDs. > > So you're saying you'd like to have the SID be <&apps_smmu 0x6c3 0x0> in > the sdm845.dtsi file and then override this on Cheza because our SID is > different (possibly because we don't use GSI)? Why can't we program the > SID in Cheza firmware to match the "HLOS" SID of 0x6c3? Sorry my bad, I missed the overriding part. May be we add the lists of SIDs in board dts only. So, cheza dts will have all these SIDs - <&apps_smmu 0x6c0 0x3> // for both 0x6c0 (TZ) and 0x6c3 (HLOS) <&apps_smmu 0x6d6 0x0> // if we want to use the GSI dma. and MTP will have <&apps_smmu 0x6c3 0x0> <&apps_smmu 0x6d6 0x0> WDUT? > > > > > P.S. > > As you rightly said, the second cell in iommus property is the mask so that > > the iommu is able to reserve all that SIDs that are covered with the > > starting SID > > and the mask. > > > > Well if 0x6c6 is another possibility maybe it should be <&apps_smmu > 0x6c0 0x7> to cover the 0x6c3 and 0x6c6 SIDs? The other SID was 0x6D6. Best regards Vivek -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
