On Tue, May 21, 2019 at 03:05:16PM +0530, Amit Kucheria wrote:
> Add device bindings for cpuidle states for cpu devices.
>
> msm8996 features 4 cpus - 2 in each cluster. However, all cpus implement
> the same microarchitecture and the two clusters only differ in the
> maximum frequency attainable by the CPUs.
>
> Signed-off-by: Amit Kucheria <amit.kucheria@xxxxxxxxxx>
> ---
> arch/arm64/boot/dts/qcom/msm8996.dtsi | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> index c761269caf80..4f2fb7885f39 100644
> --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> @@ -95,6 +95,7 @@
> compatible = "qcom,kryo";
> reg = <0x0 0x0>;
> enable-method = "psci";
> + cpu-idle-states = <&CPU_SLEEP_0>;
> next-level-cache = <&L2_0>;
> L2_0: l2-cache {
> compatible = "cache";
> @@ -107,6 +108,7 @@
> compatible = "qcom,kryo";
> reg = <0x0 0x1>;
> enable-method = "psci";
> + cpu-idle-states = <&CPU_SLEEP_0>;
> next-level-cache = <&L2_0>;
> };
>
> @@ -115,6 +117,7 @@
> compatible = "qcom,kryo";
> reg = <0x0 0x100>;
> enable-method = "psci";
> + cpu-idle-states = <&CPU_SLEEP_0>;
> next-level-cache = <&L2_1>;
> L2_1: l2-cache {
> compatible = "cache";
> @@ -127,6 +130,7 @@
> compatible = "qcom,kryo";
> reg = <0x0 0x101>;
> enable-method = "psci";
> + cpu-idle-states = <&CPU_SLEEP_0>;
> next-level-cache = <&L2_1>;
> };
>
> @@ -151,6 +155,19 @@
> };
> };
> };
> +
> + idle-states {
> + entry-method = "psci";
> +
> + CPU_SLEEP_0: cpu-sleep-0 {
> + compatible = "arm,idle-state";
> + idle-state-name = "standalone-power-collapse";
> + arm,psci-suspend-param = <0x00000004>;
> + entry-latency-us = <40>;
> + exit-latency-us = <80>;
Hello Amit,
Looking at this line of code in msm-4.14:
https://source.codeaurora.org/quic/la/kernel/msm-4.14/tree/drivers/cpuidle/lpm-levels.c?h=LA.UM.7.1.r1-14000-sm8150.0#n993
And seeing the equivalent in msm-4.4:
https://source.codeaurora.org/quic/la/kernel/msm-4.4/tree/drivers/cpuidle/lpm-levels.c?h=msm-4.4#n1080
It becomes obvious that
qcom,time-overhead == entry-latency-us + exit-latency-us
and
qcom,latency-us == exit-latency-us
which means that
entry-latency-us == qcom,time-overhead - qcom,latency-us
Using this formula, with the numbers from downstream SDM845:
https://source.codeaurora.org/quic/la/kernel/msm-4.9/tree/arch/arm64/boot/dts/qcom/sdm845-pm.dtsi?h=msm-4.9#n123
qcom,latency-us = <621>;
qcom,time-overhead = <885>;
885 - 621 = 264
we end up with the same values that Raju
has in his submission for upstream SDM845:
https://patchwork.kernel.org/patch/10953253/
entry-latency-us = <264>;
exit-latency-us = <621>;
Which for msm8996:
qcom,latency-us = <80>;
qcom,time-overhead = <210>;
gives:
entry-latency-us = <130>
exit-latency-us = <80>;
> + min-residency-us = <300>;
> + };
> + };
> };
>
> thermal-zones {
> --
> 2.17.1
>
