On 13/12/2018 15:24, Marc Gonzalez wrote:
> I'm having trouble getting UFS working on an APQ8098 MEDIABOX dev board.
> (I'm running v4.20-rc4 with a few UFS patches taken off the MSM list.)
>
> I'm hoping someone with experience with the UFSHC will spot the one thing
> missing that will make everything work!
I thought I'd try v5.0-rc1 with as few patches as required.
No miracles.
$ git ls v5.0-rc1..
1d4fc30bbf14 (HEAD -> mini50) Minimal defconfig
df1be969a877 HACK: apq8098 mediabox qcom,msm-id
186d5f863808 arm64: dts: qcom: msm8998: Add UFS nodes
a44adb54db79 arm64: dts: qcom: msm8998: Add rpmcc node
8211021a3fe5 clk: qcom: Select QCOM_GDSC with MSM_GCC_8998
f8eae753c703 clk: qcom: Add CLK_SET_RATE_PARENT for 8998 branch clocks
ee5eba66218a clk: qcom: smd: Add support for MSM8998 rpm clocks
Booting Linux on physical CPU 0x0000000000 [0x51af8014]
Linux version 5.0.0-rc1 (mgonzalez@venus) (gcc version 7.3.1 20180425 [linaro-7.3-2018.05 revision d29120a424ecfbc167ef90065c0eeb7f91977701] (Linaro GCC 7.3-2018.05)) #2 SMP PREEMPT Fri Jan 11 15:08:34 CET 2019
Machine model: Qualcomm Technologies, Inc. MSM8998 v1 MTP
On node 0 totalpages: 1028544
DMA32 zone: 8192 pages used for memmap
DMA32 zone: 0 pages reserved
DMA32 zone: 511488 pages, LIFO batch:63
Normal zone: 8079 pages used for memmap
Normal zone: 517056 pages, LIFO batch:63
psci: probing for conduit method from DT.
psci: PSCIv1.0 detected in firmware.
psci: Using standard PSCI v0.2 function IDs
psci: MIGRATE_INFO_TYPE not supported.
psci: SMC Calling Convention v1.0
random: get_random_bytes called from start_kernel+0xb0/0x450 with crng_init=0
percpu: Embedded 22 pages/cpu @(____ptrval____) s49816 r8192 d32104 u90112
pcpu-alloc: s49816 r8192 d32104 u90112 alloc=22*4096
pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3 [0] 4 [0] 5 [0] 6 [0] 7
Detected VIPT I-cache on CPU0
CPU features: detected: Kernel page table isolation (KPTI)
Built 1 zonelists, mobility grouping on. Total pages: 1012273
Kernel command line: loglevel=0 nosmp clk_ignore_unused pd_ignore_unused trace_event=ufs:*,clk:*,regulator:* tp_printk androidboot.bootdevice=1da4000.ufshc androidboot.serialno=53733c35 androidboot.baseband=apq mdss_mdp.panel=1:hdmi:16
Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes)
Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes)
software IO TLB: mapped [mem 0xfbfff000-0xfffff000] (64MB)
Memory: 3954392K/4114176K available (3262K kernel code, 394K rwdata, 924K rodata, 7232K init, 1130K bss, 159784K reserved, 0K cma-reserved)
SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
ftrace: allocating 12477 entries in 49 pages
rcu: Preemptible hierarchical RCU implementation.
rcu: RCU restricting CPUs from NR_CPUS=64 to nr_cpu_ids=8.
Tasks RCU enabled.
rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
GICv3: Distributor has no Range Selector support
GICv3: no VLPI support, no direct LPI support
GICv3: CPU0: found redistributor 0 region 0:0x0000000017b00000
ITS: No ITS available, not enabling LPIs
arch_timer: cp15 and mmio timer(s) running at 19.20MHz (virt/virt).
clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x46d987e47, max_idle_ns: 440795202767 ns
sched_clock: 56 bits at 19MHz, resolution 52ns, wraps every 4398046511078ns
Console: colour dummy device 80x25
printk: console [tty0] enabled
Calibrating delay loop (skipped), value calculated using timer frequency.. 38.40 BogoMIPS (lpj=76800)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 8192 (order: 4, 65536 bytes)
Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes)
ASID allocator initialised with 32768 entries
rcu: Hierarchical SRCU implementation.
smp: Bringing up secondary CPUs ...
smp: Brought up 1 node, 1 CPU
SMP: Total of 1 processors activated.
CPU features: detected: GIC system register CPU interface
CPU features: detected: 32-bit EL0 Support
CPU features: detected: CRC32 instructions
CPU: All CPU(s) started at EL1
alternatives: patching kernel code
devtmpfs: initialized
clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
futex hash table entries: 2048 (order: 5, 131072 bytes)
pinctrl core: initialized pinctrl subsystem
regulator_enable: name=regulator-dummy
vdso: 2 pages (1 code @ (____ptrval____), 1 data @ (____ptrval____))
DMA: preallocated 256 KiB pool for atomic allocations
clk_prepare: gcc_mmss_noc_cfg_ahb_clk
clk_prepare_complete: gcc_mmss_noc_cfg_ahb_clk
clk_enable: gcc_mmss_noc_cfg_ahb_clk
clk_enable_complete: gcc_mmss_noc_cfg_ahb_clk
regulator_enable: name=vph_pwr
SCSI subsystem initialized
clocksource: Switched to clocksource arch_sys_counter
s1: supplied by vph_pwr
s2: supplied by vph_pwr
s3: supplied by vph_pwr
s3: Bringing 0uV into 1352000-1352000uV
regulator_set_voltage: name=s3 (1352000-1352000)
regulator_set_voltage_complete: name=s3, val=320000
s4: supplied by vph_pwr
s4: Bringing 0uV into 1800000-1800000uV
regulator_set_voltage: name=s4 (1800000-1800000)
regulator_set_voltage_complete: name=s4, val=320000
s5: supplied by vph_pwr
s5: Bringing 0uV into 1904000-1904000uV
regulator_set_voltage: name=s5 (1904000-1904000)
regulator_set_voltage_complete: name=s5, val=320000
s6: supplied by vph_pwr
s7: supplied by vph_pwr
s7: Bringing 0uV into 900000-900000uV
regulator_set_voltage: name=s7 (900000-900000)
regulator_set_voltage_complete: name=s7, val=320000
s8: supplied by vph_pwr
s9: supplied by vph_pwr
s10: supplied by vph_pwr
s11: supplied by vph_pwr
s12: supplied by vph_pwr
s13: supplied by vph_pwr
l1: supplied by s7
l1: Bringing 0uV into 880000-880000uV
regulator_set_voltage: name=l1 (880000-880000)
regulator_set_voltage_complete: name=l1, val=312000
l2: supplied by s3
l2: Bringing 0uV into 1200000-1200000uV
regulator_set_voltage: name=l2 (1200000-1200000)
regulator_set_voltage_complete: name=l2, val=312000
l3: supplied by s7
l3: Bringing 0uV into 1000000-1000000uV
regulator_set_voltage: name=l3 (1000000-1000000)
regulator_set_voltage_complete: name=l3, val=312000
l4: supplied by s7
l5: supplied by s7
l5: Bringing 0uV into 800000-800000uV
regulator_set_voltage: name=l5 (800000-800000)
regulator_set_voltage_complete: name=l5, val=312000
l6: supplied by s5
l6: Bringing 0uV into 1808000-1808000uV
regulator_set_voltage: name=l6 (1808000-1808000)
regulator_set_voltage_complete: name=l6, val=1664000
l7: supplied by s5
l7: Bringing 0uV into 1800000-1800000uV
regulator_set_voltage: name=l7 (1800000-1800000)
regulator_set_voltage_complete: name=l7, val=1256000
l8: supplied by s3
l8: Bringing 0uV into 1200000-1200000uV
regulator_set_voltage: name=l8 (1200000-1200000)
regulator_set_voltage_complete: name=l8, val=312000
l9: Bringing 0uV into 1808000-1808000uV
regulator_set_voltage: name=l9 (1808000-1808000)
regulator_set_voltage_complete: name=l9, val=1664000
l10: Bringing 0uV into 1808000-1808000uV
regulator_set_voltage: name=l10 (1808000-1808000)
regulator_set_voltage_complete: name=l10, val=1664000
l11: supplied by s7
l11: Bringing 0uV into 1000000-1000000uV
regulator_set_voltage: name=l11 (1000000-1000000)
regulator_set_voltage_complete: name=l11, val=312000
l12: supplied by s5
l12: Bringing 0uV into 1800000-1800000uV
regulator_set_voltage: name=l12 (1800000-1800000)
regulator_set_voltage_complete: name=l12, val=1256000
l13: Bringing 0uV into 1808000-1808000uV
regulator_set_voltage: name=l13 (1808000-1808000)
regulator_set_voltage_complete: name=l13, val=1664000
l14: supplied by s5
l14: Bringing 0uV into 1880000-1880000uV
regulator_set_voltage: name=l14 (1880000-1880000)
regulator_set_voltage_complete: name=l14, val=1256000
l15: supplied by s5
l15: Bringing 0uV into 1800000-1800000uV
regulator_set_voltage: name=l15 (1800000-1800000)
regulator_set_voltage_complete: name=l15, val=1256000
l16: Bringing 0uV into 2704000-2704000uV
regulator_set_voltage: name=l16 (2704000-2704000)
regulator_set_voltage_complete: name=l16, val=1664000
l17: supplied by s3
l17: Bringing 0uV into 1304000-1304000uV
regulator_set_voltage: name=l17 (1304000-1304000)
regulator_set_voltage_complete: name=l17, val=312000
l18: Bringing 0uV into 2704000-2704000uV
regulator_set_voltage: name=l18 (2704000-2704000)
regulator_set_voltage_complete: name=l18, val=1664000
l19: Bringing 0uV into 3008000-3008000uV
regulator_set_voltage: name=l19 (3008000-3008000)
regulator_set_voltage_complete: name=l19, val=1664000
l20: Bringing 0uV into 2960000-2960000uV
regulator_set_voltage: name=l20 (2960000-2960000)
regulator_set_voltage_complete: name=l20, val=1664000
l21: Bringing 0uV into 2960000-2960000uV
regulator_set_voltage: name=l21 (2960000-2960000)
regulator_set_voltage_complete: name=l21, val=1664000
l22: Bringing 0uV into 2864000-2864000uV
regulator_set_voltage: name=l22 (2864000-2864000)
regulator_set_voltage_complete: name=l22, val=1664000
l23: Bringing 0uV into 3312000-3312000uV
regulator_set_voltage: name=l23 (3312000-3312000)
regulator_set_voltage_complete: name=l23, val=1664000
l24: Bringing 0uV into 3088000-3088000uV
regulator_set_voltage: name=l24 (3088000-3088000)
regulator_set_voltage_complete: name=l24, val=1664000
l25: Bringing 0uV into 3104000-3104000uV
regulator_set_voltage: name=l25 (3104000-3104000)
regulator_set_voltage_complete: name=l25, val=1664000
l26: supplied by s3
l26: Bringing 0uV into 1200000-1200000uV
regulator_set_voltage: name=l26 (1200000-1200000)
regulator_set_voltage_complete: name=l26, val=312000
l27: supplied by s7
l28: Bringing 0uV into 3008000-3008000uV
regulator_set_voltage: name=l28 (3008000-3008000)
regulator_set_voltage_complete: name=l28, val=1664000
lvs1: supplied by s4
lvs2: supplied by s4
bob: supplied by vph_pwr
bob: Bringing 0uV into 3312000-3312000uV
regulator_set_voltage: name=bob (3312000-3312000)
regulator_set_voltage_complete: name=bob, val=3312000
workingset: timestamp_bits=62 max_order=20 bucket_order=0
Block layer SCSI generic (bsg) driver version 0.4 loaded (major 253)
qcom-qmp-phy 1da7000.phy: Linked as a consumer to regulator.15
qcom-qmp-phy 1da7000.phy: Linked as a consumer to regulator.16
qcom-qmp-phy 1da7000.phy: Registered Qcom-QMP phy
Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
msm_serial c1b0000.serial: msm_serial: detected port #0
msm_serial c1b0000.serial: uartclk = 1843200
c1b0000.serial: ttyMSM0 at MMIO 0xc1b0000 (irq = 15, base_baud = 115200) is a MSM
clk_prepare: xo_board
clk_prepare_complete: xo_board
clk_prepare: xo
clk_prepare_complete: xo
clk_prepare: blsp2_uart2_apps_clk_src
clk_prepare_complete: blsp2_uart2_apps_clk_src
clk_prepare: gcc_blsp2_uart2_apps_clk
clk_prepare_complete: gcc_blsp2_uart2_apps_clk
clk_enable: xo_board
clk_enable_complete: xo_board
clk_enable: xo
clk_enable_complete: xo
clk_enable: blsp2_uart2_apps_clk_src
clk_enable_complete: blsp2_uart2_apps_clk_src
clk_enable: gcc_blsp2_uart2_apps_clk
clk_enable_complete: gcc_blsp2_uart2_apps_clk
clk_prepare: gcc_blsp2_ahb_clk
clk_prepare_complete: gcc_blsp2_ahb_clk
clk_enable: gcc_blsp2_ahb_clk
clk_enable_complete: gcc_blsp2_ahb_clk
msm_serial: console setup on port #0
clk_prepare: gpll0
clk_prepare_complete: gpll0
clk_prepare: gpll0_out_main
clk_prepare_complete: gpll0_out_main
clk_enable: gpll0
clk_enable_complete: gpll0
clk_enable: gpll0_out_main
clk_enable_complete: gpll0_out_main
clk_set_parent: blsp2_uart2_apps_clk_src gpll0_out_main
clk_set_parent_complete: blsp2_uart2_apps_clk_src gpll0_out_main
clk_set_rate: blsp2_uart2_apps_clk_src 3686400
clk_set_rate_complete: blsp2_uart2_apps_clk_src 3686400
clk_set_rate: gcc_blsp2_uart2_apps_clk 3686400
clk_set_rate_complete: gcc_blsp2_uart2_apps_clk 3686400
printk: console [ttyMSM0] enabled
msm_serial: driver initialized
ufshcd-qcom 1da4000.ufshc: ufshcd_populate_vreg: Unable to find vdd-hba-supply regulator, assuming enabled
clk_set_rate: ufs_axi_clk_src 200000000
clk_set_rate_complete: ufs_axi_clk_src 200000000
clk_set_rate: gcc_aggre1_ufs_axi_clk 200000000
clk_set_rate_complete: gcc_aggre1_ufs_axi_clk 200000000
clk_set_rate: gcc_ufs_axi_clk 200000000
clk_set_rate_complete: gcc_ufs_axi_clk 200000000
clk_prepare: ufs_axi_clk_src
clk_prepare_complete: ufs_axi_clk_src
clk_prepare: gcc_ufs_axi_clk
clk_prepare_complete: gcc_ufs_axi_clk
clk_enable: ufs_axi_clk_src
clk_enable_complete: ufs_axi_clk_src
clk_enable: gcc_ufs_axi_clk
clk_enable_complete: gcc_ufs_axi_clk
clk_prepare: gcc_aggre1_ufs_axi_clk
clk_prepare_complete: gcc_aggre1_ufs_axi_clk
clk_enable: gcc_aggre1_ufs_axi_clk
clk_enable_complete: gcc_aggre1_ufs_axi_clk
clk_prepare: gcc_ufs_ahb_clk
clk_prepare_complete: gcc_ufs_ahb_clk
clk_enable: gcc_ufs_ahb_clk
clk_enable_complete: gcc_ufs_ahb_clk
clk_prepare: gcc_ufs_unipro_core_clk
clk_prepare_complete: gcc_ufs_unipro_core_clk
clk_enable: gcc_ufs_unipro_core_clk
clk_enable_complete: gcc_ufs_unipro_core_clk
clk_prepare: gcc_ufs_ice_core_clk
clk_prepare_complete: gcc_ufs_ice_core_clk
clk_enable: gcc_ufs_ice_core_clk
clk_enable_complete: gcc_ufs_ice_core_clk
clk_prepare: ln_bb_clk1
clk_prepare_complete: ln_bb_clk1
clk_enable: ln_bb_clk1
clk_enable_complete: ln_bb_clk1
clk_prepare: gcc_ufs_tx_symbol_0_clk
clk_prepare_complete: gcc_ufs_tx_symbol_0_clk
clk_enable: gcc_ufs_tx_symbol_0_clk
clk_enable_complete: gcc_ufs_tx_symbol_0_clk
clk_prepare: gcc_ufs_rx_symbol_0_clk
clk_prepare_complete: gcc_ufs_rx_symbol_0_clk
clk_enable: gcc_ufs_rx_symbol_0_clk
clk_enable_complete: gcc_ufs_rx_symbol_0_clk
clk_prepare: gcc_ufs_rx_symbol_1_clk
clk_prepare_complete: gcc_ufs_rx_symbol_1_clk
clk_enable: gcc_ufs_rx_symbol_1_clk
clk_enable_complete: gcc_ufs_rx_symbol_1_clk
ufshcd_clk_gating: 1da4000.ufshc: gating state changed to CLKS_ON
ufshcd_profile_clk_gating: 1da4000.ufshc: on: took 771 usecs, err 0
l20: supplied by bob
ufshcd-qcom 1da4000.ufshc: Linked as a consumer to regulator.34
ufshcd-qcom 1da4000.ufshc: Linked as a consumer to regulator.40
ufshcd-qcom 1da4000.ufshc: Linked as a consumer to regulator.5
regulator_enable: name=bob
regulator_enable_delay: name=bob
regulator_enable_complete: name=bob
regulator_enable: name=l20
regulator_enable_delay: name=l20
regulator_enable_complete: name=l20
regulator_enable: name=s3
regulator_enable_delay: name=s3
regulator_enable_complete: name=s3
regulator_enable: name=l26
regulator_enable_delay: name=l26
regulator_enable_complete: name=l26
regulator_enable: name=s4
regulator_enable_delay: name=s4
regulator_enable_complete: name=s4
scsi host0: ufshcd
regulator_enable: name=s7
regulator_enable_delay: name=s7
regulator_enable_complete: name=s7
regulator_enable: name=l1
regulator_enable_delay: name=l1
regulator_enable_complete: name=l1
regulator_enable: name=l2
regulator_enable_delay: name=l2
regulator_enable_complete: name=l2
clk_prepare: gcc_ufs_clkref_clk
clk_prepare_complete: gcc_ufs_clkref_clk
clk_prepare: gcc_ufs_phy_aux_clk
clk_prepare_complete: gcc_ufs_phy_aux_clk
clk_enable: gcc_ufs_clkref_clk
clk_enable_complete: gcc_ufs_clkref_clk
clk_enable: gcc_ufs_phy_aux_clk
clk_enable_complete: gcc_ufs_phy_aux_clk
ufshcd-qcom 1da4000.ufshc: ufshcd_print_pwr_info:[RX, TX]: gear=[1, 1], lane[1, 1], pwr[SLOWAUTO_MODE, SLOWAUTO_MODE], rate = 0
ufshcd_upiu: query_send: 1da4000.ufshc: HDR:00 00 00 1f 00 00 00 00 00 00 00 00, CDB:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
ufshcd_command: send: 1da4000.ufshc: tag: 31, DB: 0x80000000, size: -1, IS: 0, LBA: 18446744073709551615, opcode: 0x0
ufshcd_command: dev_complete: 1da4000.ufshc: tag: 31, DB: 0x0, size: -1, IS: 0, LBA: 18446744073709551615, opcode: 0x0
ufshcd_upiu: query_complete: 1da4000.ufshc: HDR:00 00 00 1f 00 00 00 00 00 00 00 00, CDB:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
ufshcd_upiu: query_send: 1da4000.ufshc: HDR:16 00 00 1f 00 81 00 00 00 00 00 00, CDB:06 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00
ufshcd_command: send: 1da4000.ufshc: tag: 31, DB: 0x80000000, size: -1, IS: 0, LBA: 18446744073709551615, opcode: 0x0
genpd: Not disabling unused power domains
clk: Not disabling unused clocks
l9: supplied by bob
l10: supplied by bob
l13: supplied by bob
l16: supplied by bob
l18: supplied by bob
l19: supplied by bob
l21: supplied by bob
l22: supplied by bob
l23: supplied by bob
l24: supplied by bob
l25: supplied by bob
l28: supplied by bob
clk_set_rate: blsp2_uart2_apps_clk_src 3686400
clk_set_rate_complete: blsp2_uart2_apps_clk_src 3686400
clk_set_rate: gcc_blsp2_uart2_apps_clk 3686400
clk_set_rate_complete: gcc_blsp2_uart2_apps_clk 3686400
ufshcd_upiu: query_complete_err: 1da4000.ufshc: HDR:16 00 00 1f 00 81 00 00 00 00 00 00, CDB:06 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00
ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag: Sending flag query for idn 1 failed, err = -11
ufshcd_upiu: query_send: 1da4000.ufshc: HDR:16 00 00 1f 00 81 00 00 00 00 00 00, CDB:06 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00
ufshcd_command: send: 1da4000.ufshc: tag: 31, DB: 0x80000000, size: -1, IS: 0, LBA: 18446744073709551615, opcode: 0x0
ufshcd_upiu: query_complete_err: 1da4000.ufshc: HDR:16 00 00 1f 00 81 00 00 00 00 00 00, CDB:06 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00
ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag: Sending flag query for idn 1 failed, err = -11
ufshcd_upiu: query_send: 1da4000.ufshc: HDR:16 00 00 1f 00 81 00 00 00 00 00 00, CDB:06 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00
ufshcd_command: send: 1da4000.ufshc: tag: 31, DB: 0x80000000, size: -1, IS: 0, LBA: 18446744073709551615, opcode: 0x0
ufshcd_upiu: query_complete_err: 1da4000.ufshc: HDR:16 00 00 1f 00 81 00 00 00 00 00 00, CDB:06 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00
ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag: Sending flag query for idn 1 failed, err = -11
ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag_retry: query attribute, opcode 6, idn 1, failed with error -11 after 3 retires
ufshcd-qcom 1da4000.ufshc: ufshcd_complete_dev_init setting fDeviceInit flag failed with error -11
clk_disable: gcc_ufs_phy_aux_clk
clk_disable_complete: gcc_ufs_phy_aux_clk
clk_disable: gcc_ufs_clkref_clk
clk_disable_complete: gcc_ufs_clkref_clk
clk_unprepare: gcc_ufs_phy_aux_clk
clk_unprepare_complete: gcc_ufs_phy_aux_clk
clk_unprepare: gcc_ufs_clkref_clk
clk_unprepare_complete: gcc_ufs_clkref_clk
regulator_disable: name=l2
regulator_disable_complete: name=l2
regulator_disable: name=l1
regulator_disable_complete: name=l1
regulator_disable: name=s7
regulator_disable_complete: name=s7
regulator_disable: name=l20
regulator_disable_complete: name=l20
regulator_disable: name=bob
regulator_disable_complete: name=bob
regulator_disable: name=l26
regulator_disable_complete: name=l26
regulator_disable: name=s3
regulator_disable_complete: name=s3
regulator_disable: name=s4
regulator_disable_complete: name=s4
clk_disable: gcc_ufs_axi_clk
clk_disable_complete: gcc_ufs_axi_clk
clk_unprepare: gcc_ufs_axi_clk
clk_unprepare_complete: gcc_ufs_axi_clk
clk_disable: gcc_aggre1_ufs_axi_clk
clk_disable_complete: gcc_aggre1_ufs_axi_clk
clk_disable: ufs_axi_clk_src
clk_disable_complete: ufs_axi_clk_src
clk_unprepare: gcc_aggre1_ufs_axi_clk
clk_unprepare_complete: gcc_aggre1_ufs_axi_clk
clk_unprepare: ufs_axi_clk_src
clk_unprepare_complete: ufs_axi_clk_src
clk_disable: gcc_ufs_ahb_clk
clk_disable_complete: gcc_ufs_ahb_clk
clk_unprepare: gcc_ufs_ahb_clk
clk_unprepare_complete: gcc_ufs_ahb_clk
clk_disable: gcc_ufs_unipro_core_clk
clk_disable_complete: gcc_ufs_unipro_core_clk
clk_unprepare: gcc_ufs_unipro_core_clk
clk_unprepare_complete: gcc_ufs_unipro_core_clk
clk_disable: gcc_ufs_ice_core_clk
clk_disable_complete: gcc_ufs_ice_core_clk
clk_unprepare: gcc_ufs_ice_core_clk
clk_unprepare_complete: gcc_ufs_ice_core_clk
clk_disable: ln_bb_clk1
clk_disable_complete: ln_bb_clk1
clk_unprepare: ln_bb_clk1
clk_unprepare_complete: ln_bb_clk1
clk_disable: gcc_ufs_tx_symbol_0_clk
clk_disable_complete: gcc_ufs_tx_symbol_0_clk
clk_unprepare: gcc_ufs_tx_symbol_0_clk
clk_unprepare_complete: gcc_ufs_tx_symbol_0_clk
clk_disable: gcc_ufs_rx_symbol_0_clk
clk_disable_complete: gcc_ufs_rx_symbol_0_clk
clk_unprepare: gcc_ufs_rx_symbol_0_clk
clk_unprepare_complete: gcc_ufs_rx_symbol_0_clk
clk_disable: gcc_ufs_rx_symbol_1_clk
clk_disable_complete: gcc_ufs_rx_symbol_1_clk
clk_unprepare: gcc_ufs_rx_symbol_1_clk
clk_unprepare_complete: gcc_ufs_rx_symbol_1_clk
ufshcd_profile_clk_gating: 1da4000.ufshc: off: took 489 usecs, err 0
ufshcd_init: 1da4000.ufshc: took 4537882 usecs, dev_state: UFS_ACTIVE_PWR_MODE, link_state: UIC_LINK_ACTIVE_STATE, err -11
