On Wed, Jun 20, 2018 at 12:57:30PM +0530, Abhishek Sahu wrote: > 1. If nand-ecc-strength specified in DT, then controller will use > this ECC strength otherwise ECC strength will be calculated > according to chip requirement and available OOB size. > > 2. QCOM NAND controller supports only one step size (512 bytes) but > nand-ecc-step-size is required property in DT. This DT property > can be removed and ecc step size can be assigned in driver with > 512 bytes value. > > Signed-off-by: Abhishek Sahu <absahu@xxxxxxxxxxxxxx> > --- > > * Changes from v3: > > 1. Clubbed following 2 patches into one > https://patchwork.ozlabs.org/patch/920465/ > https://patchwork.ozlabs.org/patch/920467/ > > * Changes from v2: > NONE > > * Changes from v1: > NEW PATCH > > Documentation/devicetree/bindings/mtd/qcom_nandc.txt | 7 +++---- > 1 file changed, 3 insertions(+), 4 deletions(-) Reviewed-by: Rob Herring <robh@xxxxxxxxxx> -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
