On 11/14/2017 04:03 AM, Linus Walleij wrote:
The more intrusive design is on my request so I will look at it in detail
ASAP. I took a quick look and liked what I saw, I just need to make
sure about the details. Also it'd be nice to have a nod from Björn.
The main reason for some of the work is ACPI, am I right?
Yes. We don't have a nice hierarchical tree that lists the individual
pins and their purposes. We just have a dumb list of GPIOs.
Timur could you look quickly at the series posted by Andy Shevchenko
(6 patches prefixed gpiolib: acpi: ) for augmenting ACPI GPIOs in the core?
Especially patch 5 and 6 which introduce the ability to add quirks in the
core.
So this is something that I've never really understood with
gpiolib-acpi. I don't think this file is used with the pin control driver.
We do have GpioInt and GpioIo statements in our GPIO table, but they
don't appear to be using the TLMM (our GPIO / pin control device)
For example:
GpioInt(Level, ActiveHigh, Exclusive, PullNone, , "\\_SB.TCS0.QIC5") {10}
The \\_SB.TCS0 device is NOT the TLMM. It's our "irq combiner" which
has something to do with performance measurement. I think the
I don't think Andy's patch set has anything to do with my patches. My
patches just try to register a GPIO device, whereas the gpiolib-acpi
patches are about ACPI nodes performing gpio-like operations.
I'd like to get some ARM-based people to look at it to make sure we
those systems can also quirk their GPIOs if need be.
My patches aren't about a quirk. All I'm trying to do is registers
specific GPIOs rather than one giant block of them.
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