[].. >> static int gdsc_toggle_logic(struct gdsc *sc, bool en) >> { >> int ret; >> @@ -164,16 +171,28 @@ static int gdsc_enable(struct generic_pm_domain *domain) >> */ >> udelay(1); >> >> + /* Turn on HW trigger mode if supported */ >> + if (sc->flags & HW_CTRL) >> + return gdsc_hwctrl(sc, true); >> + >> return 0; >> } >> >> static int gdsc_disable(struct generic_pm_domain *domain) >> { >> struct gdsc *sc = domain_to_gdsc(domain); >> + int ret; >> >> if (sc->pwrsts == PWRSTS_ON) >> return gdsc_assert_reset(sc); >> >> + /* Turn off HW trigger mode if supported */ >> + if (sc->flags & HW_CTRL) { >> + ret = gdsc_hwctrl(sc, false); > > Looking in the downstream implementation the disabling of the hw control > bit shouldn't be enough. > > After disabling hw control bit we must have a 1us delay and polling for > enabled PWR_ON bit with timeout of 100us, only then we should continue > with disabling the GDSC in software controlled mode. Stan, thats right. I will send a patch to fix this up right-away. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html