On Mon, Feb 24, 2025 at 12:46:44PM +0100, Konrad Dybcio wrote: > On 24.02.2025 9:46 AM, Wenbin Yao (Consultant) wrote: > > On 2/24/2025 3:33 PM, Manivannan Sadhasivam wrote: > >> On Thu, Feb 20, 2025 at 06:22:53PM +0800, Wenbin Yao wrote: > >>> From: Qiang Yu <quic_qianyu@xxxxxxxxxxx> > >>> > >>> Some QCOM PCIe PHYs support no_csr reset. Unlike BCR reset which resets the > >>> whole PHY (hardware and register), no_csr reset only resets PHY hardware > >>> but retains register values, which means PHY setting can be skipped during > >>> PHY init if PCIe link is enabled in booltloader and only no_csr is toggled > >>> after that. > >>> > >>> Hence, determine whether the PHY has been enabled in bootloader by > >>> verifying QPHY_START_CTRL register. If it's programmed and no_csr reset is > >>> available, skip BCR reset and PHY register setting to establish the PCIe > >>> link with bootloader - programmed PHY settings. > >>> > >>> Signed-off-by: Qiang Yu <quic_qianyu@xxxxxxxxxxx> > >>> Signed-off-by: Wenbin Yao <quic_wenbyao@xxxxxxxxxxx> > >> Some nitpicks below. > >> > >>> --- > > [...] > > >> > >>> + * In this way, no matter whether the PHY settings were initially > >>> + * programmed by bootloader or PHY driver itself, we can reuse them > >> It is really possible to have bootloader not programming the init sequence for > >> no_csr reset platforms? The comment sounds like it is possible. But I heard the > >> opposite. > > > > PCIe3 on X1E80100 QCP is disabled by default in UEFI. We need to enable it > > manually in UEFI shell if we want. > > IIUC this will not be a concern going forward, and this is a special case > I'm wondering how many *special* cases we may have to deal with going forward. Anyhow, I would propose to atleast throw an error and fail probe() if: * the platform has no_csr reset AND * bootloader has not initialized the PHY AND * there are no init sequences in the kernel - Mani -- மணிவண்ணன் சதாசிவம்
