On Wed, Feb 19, 2025 at 05:23:32PM +0100, Krzysztof Kozlowski wrote: > Newly added dsi_pll_cmn_clk_cfg1_update() wrapper protects concurrent > updates to PHY_CMN_CLK_CFG1 register between driver and Common Clock > Framework. pll_7nm_register() still used in one place previous > readl+writel, which can be simplified with this new wrapper. > > This is purely for readability and simplification and should have no > functional impact, because the code touched here is before clock is > registered via CCF, so there is no concurrency issue. > > Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx> > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> > --- > > Changes in v5: > 1. New patch > --- > drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 8 +++----- > drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml | 1 + > 2 files changed, 4 insertions(+), 5 deletions(-) > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx> -- With best wishes Dmitry
