Changes in v5: - Drop applied patches 1-3 - Split part touching pll_7nm_register() from last (#4) patch to new patch - Thus: new patch #1 in new numbering. - Link to v4: https://lore.kernel.org/r/20250217-drm-msm-phy-pll-cfg-reg-v4-0-106b0d1df51e@xxxxxxxxxx Changes in v4: - Add tags - Patch #4: Add mising bitfield.h include - One more FIELD_GET and DSI_7nm_PHY_CMN_CLK_CFG1_DSICLK_SEL (Dmitry) - Link to v3: https://lore.kernel.org/r/20250214-drm-msm-phy-pll-cfg-reg-v3-0-0943b850722c@xxxxxxxxxx Changes in v3: - Define bitfields in patches 1-3, so move there parts from patch #4 - Use FIELD_GET - Keep separate cached->bit_clk_div and pix_clk_div - I think this implements entire feedback from Dmitry - Link to v2: https://lore.kernel.org/r/20250203-drm-msm-phy-pll-cfg-reg-v2-0-862b136c5d22@xxxxxxxxxx Changes in v2: - Add Fixes tag - New patch #4 - Link to v1: https://lore.kernel.org/r/20250131-drm-msm-phy-pll-cfg-reg-v1-0-3b99efeb2e8d@xxxxxxxxxx Calling these improvements, not fixes, because I don't think we ever hit actual concurrency issue. Although if we ever hit it, it would be very tricky to debug and find the cause. Best regards, Krzysztof --- Krzysztof Kozlowski (2): drm/msm/dsi/phy: Use dsi_pll_cmn_clk_cfg1_update() when registering PLL drm/msm/dsi/phy: Define PHY_CMN_CLK_CFG[01] bitfields and simplify saving drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 18 +++++++++--------- drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml | 1 + 2 files changed, 10 insertions(+), 9 deletions(-) --- base-commit: 15ad9d0efd6a8b1db4c098ac0a5e66b736ca774a change-id: 20250131-drm-msm-phy-pll-cfg-reg-7e5bf5aa9df6 Best regards, -- Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
