On Mon, Feb 17, 2025 at 05:41:32PM +0100, Krzysztof Kozlowski wrote: > Add support for DSI PHY v7.0 on Qualcomm SM8750 SoC which comes with an > incompatible hardware interface change: > > ICODE_ACCUM_STATUS_LOW and ALOG_OBSV_BUS_STATUS_1 registers - their > offsets were just switched. Currently these registers are not used in > the driver, so the easiest is to document both but keep them commented > out to avoid conflict. > > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> > > --- > > Changes in v2: > 1. :-) > --- > drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 + > drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 + > drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 79 ++++++++++++++++++++-- > .../gpu/drm/msm/registers/display/dsi_phy_7nm.xml | 14 ++++ > 4 files changed, 90 insertions(+), 6 deletions(-) > > @@ -191,11 +192,24 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> > <reg32 offset="0x01b0" name="COMMON_STATUS_ONE"/> > <reg32 offset="0x01b4" name="COMMON_STATUS_TWO"/> > <reg32 offset="0x01b8" name="BAND_SEL_CAL"/> > + <!-- > + Starting from SM8750, offset moved from 0x01bc to 0x01cc, however > + we keep only one register map. That's not a problem, so far, > + because this register is not used. The register map should be split > + once it is going to be used. Comment out the code to prevent > + any misuse due to the change in the offset. Mumbles a lot about the hardware design. > <reg32 offset="0x01bc" name="ICODE_ACCUM_STATUS_LOW"/> > + <reg32 offset="0x01cc" name="ICODE_ACCUM_STATUS_LOW"/> > + --> > <reg32 offset="0x01c0" name="ICODE_ACCUM_STATUS_HIGH"/> > <reg32 offset="0x01c4" name="FD_OUT_LOW"/> > <reg32 offset="0x01c8" name="FD_OUT_HIGH"/> > + <!-- > + Starting from SM8750, offset moved from 0x01cc to 0x01bc, however > + we keep only one register map. See above comment. > <reg32 offset="0x01cc" name="ALOG_OBSV_BUS_STATUS_1"/> > + <reg32 offset="0x01bc" name="ALOG_OBSV_BUS_STATUS_1"/> > + --> > <reg32 offset="0x01d0" name="PLL_MISC_CONFIG"/> > <reg32 offset="0x01d4" name="FLL_CONFIG"/> > <reg32 offset="0x01d8" name="FLL_FREQ_ACQ_TIME"/> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx> -- With best wishes Dmitry
