On 14/02/2025 16:08, Krzysztof Kozlowski wrote: > Add bitfields for PHY_CMN_CLK_CFG0 and PHY_CMN_CLK_CFG1 registers to > avoid hard-coding bit masks and shifts and make the code a bit more > readable. While touching the lines in dsi_7nm_pll_save_state() > resulting cached->pix_clk_div assignment would be too big, so just > combine pix_clk_div and bit_clk_div into one cached state to make > everything simpler. > > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> > > --- > > Changes in v3: > 1. Use FIELD_GET I have LKP build reports here, so this or some earlier patches need bitfield.h header. Best regards, Krzysztof
