Changes in v3: - Define bitfields in patches 1-3, so move there parts from patch #4 - Use FIELD_GET - Keep separate cached->bit_clk_div and pix_clk_div - I think this implements entire feedback from Dmitry - Link to v2: https://lore.kernel.org/r/20250203-drm-msm-phy-pll-cfg-reg-v2-0-862b136c5d22@xxxxxxxxxx Changes in v2: - Add Fixes tag - New patch #4 - Link to v1: https://lore.kernel.org/r/20250131-drm-msm-phy-pll-cfg-reg-v1-0-3b99efeb2e8d@xxxxxxxxxx Calling these improvements, not fixes, because I don't think we ever hit actual concurrency issue. Although if we ever hit it, it would be very tricky to debug and find the cause. Best regards, Krzysztof --- Krzysztof Kozlowski (4): drm/msm/dsi/phy: Protect PHY_CMN_CLK_CFG0 updated from driver side drm/msm/dsi/phy: Protect PHY_CMN_CLK_CFG1 against clock driver drm/msm/dsi/phy: Do not overwite PHY_CMN_CLK_CFG1 when choosing bitclk source drm/msm/dsi/phy: Define PHY_CMN_CLK_CFG[01] bitfields and simplify saving drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 63 ++++++++++++++-------- .../gpu/drm/msm/registers/display/dsi_phy_7nm.xml | 12 ++++- 2 files changed, 52 insertions(+), 23 deletions(-) --- base-commit: 883d3876ff4bb50d1b9431f525b4d3b257ead6f5 change-id: 20250131-drm-msm-phy-pll-cfg-reg-7e5bf5aa9df6 Best regards, -- Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
