On 2/14/2025 7:08 AM, Krzysztof Kozlowski wrote:
PHY_CMN_CLK_CFG1 register is updated by the PHY driver and by a mux
clock from Common Clock Framework:
devm_clk_hw_register_mux_parent_hws(). There could be a path leading to
concurrent and conflicting updates between PHY driver and clock
framework, e.g. changing the mux and enabling PLL clocks.
Add dedicated spinlock to be sure all PHY_CMN_CLK_CFG1 updates are
synchronized.
While shuffling the code, define and use PHY_CMN_CLK_CFG1 bitfields to
make the code more readable and obvious.
Fixes: 1ef7c99d145c ("drm/msm/dsi: add support for 7nm DSI PHY/PLL")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
---
Changes in v3:
1. Define bitfields (move here parts from patch #4)
Changes in v2:
1. Store BIT(4) and BIT(5) in local var in dsi_pll_enable_global_clk()
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 35 ++++++++++++++--------
.../gpu/drm/msm/registers/display/dsi_phy_7nm.xml | 5 +++-
2 files changed, 26 insertions(+), 14 deletions(-)
Reviewed-by: Abhinav Kumar <quic_abhinavk@xxxxxxxxxxx>
