Hi Lijuan, thanks for your patches! On Thu, Dec 19, 2024 at 9:00 AM Lijuan Gao <quic_lijuang@xxxxxxxxxxx> wrote: > The UFS_RESET pin on Qualcomm SoCs are controlled by TLMM and exposed > through the GPIO framework. It is expected to be wired to the reset pin > of the primary UFS memory so that the UFS driver can toggle it. > > The UFS_RESET pin is exported as GPIOs in addtion to the real GPIOs. The > QCS615 TLMM pin controller has GPIOs 0-122, so correct the gpio-rangs to > 124. The QCS8300 TLMM pin controller has GPIOs 0-132, so correct the > gpio-rangs to 134. (...) > Lijuan Gao (6): > dt-bindings: pinctrl: qcom: correct gpio-ranges in examples for qcs615 > dt-bindings: pinctrl: qcom: correct gpio-ranges in examples for qcs8300 > pinctrl: qcom: correct the ngpios entry for QCS615 > pinctrl: qcom: correct the ngpios entry for QCS8300 I'm planning to apply these 4 after v3 arrives with the collected ACKs etc. Yours, Linus Walleij
