On 25.11.2024 3:20 AM, Yuanjie Yang wrote: > On Fri, Nov 22, 2024 at 01:35:28PM +0100, Krzysztof Kozlowski wrote: >> On 22/11/2024 09:40, Yuanjie Yang wrote: >>> On Fri, Nov 22, 2024 at 08:04:31AM +0100, Krzysztof Kozlowski wrote: >>>> On 22/11/2024 07:51, Yuanjie Yang wrote: >>>>> Add SDHC1 and SDHC2 support to the QCS615 Ride platform. >>>>> >>>>> Signed-off-by: Yuanjie Yang <quic_yuanjiey@xxxxxxxxxxx> >>>>> --- [...] >>>>> + bus-width = <8>; >>>>> + qcom,dll-config = <0x000f642c>; >>>>> + qcom,ddr-config = <0x80040868>; >>>>> + supports-cqe; >>>>> + dma-coherent; >>>>> + mmc-ddr-1_8v; >>>>> + mmc-hs200-1_8v; >>>>> + mmc-hs400-1_8v; >>>>> + mmc-hs400-enhanced-strobe; >>>> >>>> These are properties of memory, not SoC. If the node is disabled, means >>>> memory is not attached to the SoC, right? >>>> >>>>> + status = "disabled"; >>> Thanks, I think qcom,dll-config and qcom,ddr-config are properties of Soc, >>> they are memory configurations that need to be written to the ioaddr. >>> And mmc-ddr-1_8v,mmc-hs200-1_8v,mmc-hs400-1_8v are bus speed config, >>> they indicate the bus speed at which the host contoller can operate. >>> If the node is disabled, which means Soc don't support these properties. >> No, that is not the meaning of node is disabled. When node is disabled, >> it means board does not have attached memory. >> >> Move the memory related properties to the board. > > Thanks, Ok I understand, I will move the memory related > properties(qcom,dll-config and qcom,ddr-config) to the > board dts in next version. DDR/DLL tuning seem to be done per SoC and not per board. Konrad
