PCIe equalization presets are predefined settings used to optimize signal integrity by compensating for signal loss and distortion in high-speed data transmission. As per PCIe spec 6.0.1 revision section 8.3.3.3 & 4.2.4 for data rates of 8.0 GT/s, 16.0 GT/s, 32.0 GT/s, and 64.0 GT/s, there is a way to configure lane equalization presets for each lane to enhance the PCIe link reliability. Each preset value represents a different combination of pre-shoot and de-emphasis values. For each data rate, different registers are defined: for 8.0 GT/s, registers are defined in section 7.7.3.4; for 16.0 GT/s, in section 7.7.5.9, etc. The 8.0 GT/s rate has an extra receiver preset hint, requiring 16 bits per lane, while the remaining data rates use 8 bits per lane. Based on the number of lanes and the supported data rate, read the device tree property and stores in the presets structure. Based upon the lane width and supported data rate update lane equalization registers. This patch depends on the this dt binding pull request: https://github.com/devicetree-org/dt-schema/pull/146 Signed-off-by: Krishna chaitanya chundru <quic_krichai@xxxxxxxxxxx> --- Krishna chaitanya chundru (4): arm64: dts: qcom: x1e80100: Add PCIe lane equalization preset properties PCI: of: Add API to retrieve equalization presets from device tree PCI: dwc: Improve handling of PCIe lane configuration PCI: dwc: Add support for configuring lane equalization presets arch/arm64/boot/dts/qcom/x1e80100.dtsi | 8 +++ drivers/pci/controller/dwc/pcie-designware-host.c | 42 +++++++++++++++ drivers/pci/controller/dwc/pcie-designware.c | 14 ++++- drivers/pci/controller/dwc/pcie-designware.h | 4 ++ drivers/pci/of.c | 62 +++++++++++++++++++++++ drivers/pci/pci.h | 17 ++++++- include/uapi/linux/pci_regs.h | 3 ++ 7 files changed, 147 insertions(+), 3 deletions(-) --- base-commit: 81983758430957d9a5cb3333fe324fd70cf63e7e change-id: 20241030-presets-ec11a3e44ab3 Best regards, -- Krishna chaitanya chundru <quic_krichai@xxxxxxxxxxx>
