On Fri, Oct 25, 2024 at 09:20:37AM +0300, Dmitry Baryshkov wrote:
> On Mon, Oct 21, 2024 at 10:22:01PM +0200, Gabor Juhos wrote:
> > Since both the 'alpha' and 'alpha_hi' members of the configuration is
> > initialized (the latter is implicitly) with zero values, the output
> > rate of the PLL will be the same whether alpha mode is enabled or not.
> >
> > Remove the initialization of the alpha* members to make it clear that
> > the alpha mode is not required to get the desired output rate.
> >
> > No functional changes intended, compile tested only.
> >
> > Signed-off-by: Gabor Juhos <j4g8y7@xxxxxxxxx>
> > ---
> > drivers/clk/qcom/dispcc-sm6115.c | 2 --
> > 1 file changed, 2 deletions(-)
> >
> > diff --git a/drivers/clk/qcom/dispcc-sm6115.c b/drivers/clk/qcom/dispcc-sm6115.c
> > index 939887f82ecc3da21a5f26168c3161aa8cfeb3cb..2b236d52b29fe72b8979da85c8bd4bfd1db54c0b 100644
> > --- a/drivers/clk/qcom/dispcc-sm6115.c
> > +++ b/drivers/clk/qcom/dispcc-sm6115.c
> > @@ -48,8 +48,6 @@ static const struct pll_vco spark_vco[] = {
> > /* 768MHz configuration */
> > static const struct alpha_pll_config disp_cc_pll0_config = {
> > .l = 0x28,
> > - .alpha = 0x0,
> > - .alpha_en_mask = BIT(24),
>
> NAK, this isn't a fixed rate PLL.
clk_alpha_pll_set_rate() hadnles this bit.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
>
> > .vco_val = 0x2 << 20,
> > .vco_mask = GENMASK(21, 20),
> > .main_output_mask = BIT(0),
> >
> > --
> > 2.47.0
> >
>
> --
> With best wishes
> Dmitry
--
With best wishes
Dmitry
