From: Konrad Dybcio <quic_kdybcio@xxxxxxxxxxx>
On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent
pagetable walk via the IDR0 register. This however is not respected by
the arm-smmu driver unless dma-coherent is set.
Mark the node as dma-coherent to ensure this (and other) implementations
take this coherency into account.
Signed-off-by: Konrad Dybcio <quic_kdybcio@xxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 54077549b9da7f0ece69a01d370692d9d716bbb5..49440d1b2cf6caf6da9d97c635cbd751f0700326 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -5159,6 +5159,7 @@ apps_smmu: iommu@15000000 {
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
};
anoc_1_tbu: tbu@150c5000 {
--
2.46.1
