On 30-08-24, 12:01, Krzysztof Kozlowski wrote: > On 29/08/2024 21:05, Vinod Koul wrote: > > > > On Fri, 23 Aug 2024 10:04:14 +0300, Abel Vesa wrote: > >> On all X Elite boards currently supported upstream, the NVMe sits > >> on the PCIe 6. Until now that has been configured in dual lane mode > >> only. The schematics reveal that the NVMe is actually using 4 lanes. > >> So add support for the 4-lane mode and document the compatible for it. > >> > >> This patchset depends on: > >> https://lore.kernel.org/all/20240805-phy-qcom-qmp-pcie-write-all-tbls-second-port-v3-1-6967c6bf61d1@xxxxxxxxxx/ > >> > >> [...] > > > > Applied, thanks! > > > > [1/2] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 QMP PCIe PHY Gen4 x4 > > commit: 0c5f4d23f77631f657b60ef660676303f7620688 > > Heh, we discussed yesterday on IRC that this should wait. I must have miseed that... > Why do we keep discussing things in private... This ideally should have followed up as a reply to this thread... -- ~Vinod
