On 8/30/24 10:25 PM, Rob Clark wrote:
On Fri, Aug 30, 2024 at 8:33 AM Antonino Maniscalco
<antomani103@xxxxxxxxx> wrote:
This patch implements preemption feature for A6xx targets, this allows
the GPU to switch to a higher priority ringbuffer if one is ready. A6XX
hardware as such supports multiple levels of preemption granularities,
ranging from coarse grained(ringbuffer level) to a more fine grained
such as draw-call level or a bin boundary level preemption. This patch
enables the basic preemption level, with more fine grained preemption
support to follow.
Signed-off-by: Sharat Masetty <smasetty@xxxxxxxxxxxxxx>
Signed-off-by: Antonino Maniscalco <antomani103@xxxxxxxxx>
Tested-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx> # on SM8650-QRD
---
drivers/gpu/drm/msm/Makefile | 1 +
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 323 +++++++++++++++++++++-
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 168 ++++++++++++
drivers/gpu/drm/msm/adreno/a6xx_preempt.c | 431 ++++++++++++++++++++++++++++++
drivers/gpu/drm/msm/msm_ringbuffer.h | 7 +
5 files changed, 921 insertions(+), 9 deletions(-)
[snip]
@@ -784,6 +1062,16 @@ static int a6xx_ucode_load(struct msm_gpu *gpu)
msm_gem_object_set_name(a6xx_gpu->shadow_bo, "shadow");
}
+ a6xx_gpu->pwrup_reglist_ptr = msm_gem_kernel_new(gpu->dev, PAGE_SIZE,
+ MSM_BO_WC | MSM_BO_MAP_PRIV,
+ gpu->aspace, &a6xx_gpu->pwrup_reglist_bo,
+ &a6xx_gpu->pwrup_reglist_iova);
I guess this could also be MSM_BO_GPU_READONLY?
BR,
-R
Besides containing the the actual reglist this buffer also contains the
`cpu_gpu_lock` structure which is written by the SQE so adding the
`MSM_BO_GPU_READONLY` flag would cause it to fault.
Best regards,
--
Antonino Maniscalco <antomani103@xxxxxxxxx>
