On Fri, Aug 23, 2024 at 10:04:15AM GMT, Abel Vesa wrote: > The sixth PCIe instance on X1E80100 can be used in either 4-lane mode or > 2-lane mode. Document the 4-lane mode as a separate compatible. As the patches were merged, it's too late for this series, but as a note: we should think of a way to describe the PHY configuration without changing the compatibility strings. The hardware stays the same, it's just the number of lanes being wired that changes. The obvious way to handle platform-specific differences is by using num-lanes property of the PCIe host and then passing required configuration (num lanes, max speed, etc.) to the PCIe PHY via phy_configure() call. > > Reviewed-by: Krzysztof Kozlowski <krzk@xxxxxxxxxx> > Reviewed-by: Johan Hovold <johan+linaro@xxxxxxxxxx> > Signed-off-by: Abel Vesa <abel.vesa@xxxxxxxxxx> > --- > Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml > index 03dbd02cf9e7..dcf4fa55fbba 100644 > --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml > +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml > @@ -40,6 +40,7 @@ properties: > - qcom,sm8650-qmp-gen4x2-pcie-phy > - qcom,x1e80100-qmp-gen3x2-pcie-phy > - qcom,x1e80100-qmp-gen4x2-pcie-phy > + - qcom,x1e80100-qmp-gen4x4-pcie-phy > > reg: > minItems: 1 > @@ -118,6 +119,7 @@ allOf: > contains: > enum: > - qcom,sc8280xp-qmp-gen3x4-pcie-phy > + - qcom,x1e80100-qmp-gen4x4-pcie-phy > then: > properties: > reg: > @@ -169,6 +171,7 @@ allOf: > - qcom,sc8280xp-qmp-gen3x1-pcie-phy > - qcom,sc8280xp-qmp-gen3x2-pcie-phy > - qcom,sc8280xp-qmp-gen3x4-pcie-phy > + - qcom,x1e80100-qmp-gen4x4-pcie-phy > then: > properties: > clocks: > > -- > 2.34.1 > -- With best wishes Dmitry
