Re: [PATCH 3/8] phy: qcom: qmp: Add phy register and clk setting for x1e80100 PCIe3

[Qiang Yu <quic_qianyu@xxxxxxxxxxx>]

On 8/27/2024 7:38 PM, Krzysztof Kozlowski wrote:
> On Mon, Aug 26, 2024 at 11:36:26PM -0700, Qiang Yu wrote:
> >   	if (cfg->tbls.ln_shrd)
> >   		qmp->ln_shrd = base + offs->ln_shrd;
> >   
> > @@ -4424,6 +4641,9 @@ static const struct of_device_id qmp_pcie_of_match_table[] = {
> >   	}, {
> >   		.compatible = "qcom,x1e80100-qmp-gen4x2-pcie-phy",
> >   		.data = &x1e80100_qmp_gen4x2_pciephy_cfg,
> > +	}, {
> > +		.compatible = "qcom,x1e80100-qmp-gen4x8-pcie-phy",
> Undocumented compatible or your patch order is wrong.
OK, will put the yaml patch in front of this patch

Thanks,
Qiang
> > +		.data = &x1e80100_qmp_gen4x8_pciephy_cfg,
> >   	},
> Best regards,
> Krzysztof