On Fri, Aug 23, 2024 at 8:21 AM Will Deacon <will@xxxxxxxxxx> wrote: > > On Tue, Jul 30, 2024 at 10:16:00AM -0700, Trilok Soni wrote: > > On 7/30/2024 1:50 AM, Dmitry Baryshkov wrote: > > >>>>>> SDM845's Adreno SMMU is unique in that it actually advertizes support > > >>>>>> for 16K (and 32M) pages, which doesn't hold for newer SoCs. > > > My question is about forbidding 16k pages for sdm845 only or for other > > > chips too. I'd assume that it shouldn't also work for other smmu-v2 > > > platforms. > > > > Yes, my understanding was that SMMUv2 based IPs doesn't have 16k support > > and it is only starting from SMMUv3. > > I'm not sure about that. The architecture doc for SMMUv2 talks about the > AArch64 translation regime in section 1.5 and bit 13 of SMMU_IDR2 says: > > | PTFSv8_16kB, bit[13] > | Support for 16KB translation granule size. The possible values of this bit are: > | 0 The 16KB translation granule is not supported. > | 1 The 16KB translation granule is supported. > | In SMMUv1, this bit is reserved. > > so I think Konrad's patch is about right, but if you want to extend it > to cover other implementations then that's fine too. > Perhaps that should have been "qcom's SMMUv2 based IPs doesn't have 16k support"? At any rate, 16k sizes don't appear to work on sc7180 as well. I don't really have any other data points but it wouldn't really surprise me if this applied to all qc smmu-v2 BR, -R
