On Tue, Aug 20, 2024 at 10:02:42PM +0800, Luo Jie wrote: > The CMN PLL controller provides clocks to networking hardware blocks > on Qualcomm IPQ9574 SoC. It receives input clock from the on-chip Wi-Fi, > and produces output clocks at fixed rates. These output rates are > predetermined, and are unrelated to the input clock rate. The output > clocks are supplied to the Ethernet hardware such as PPE (packet > process engine) and the externally connected switch or PHY device. > > Signed-off-by: Luo Jie <quic_luoj@xxxxxxxxxxx> > --- > .../bindings/clock/qcom,ipq9574-cmn-pll.yaml | 70 ++++++++++++++++++++++ > include/dt-bindings/clock/qcom,ipq-cmn-pll.h | 15 +++++ > 2 files changed, 85 insertions(+) > > diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml > new file mode 100644 > index 000000000000..7ad04b58a698 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml > @@ -0,0 +1,70 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm CMN PLL Clock Controller on IPQ SoC > + > +maintainers: > + - Bjorn Andersson <andersson@xxxxxxxxxx> > + - Luo Jie <quic_luoj@xxxxxxxxxxx> > + > +description: > + The CMN PLL clock controller expects a reference input clock. You did not explain what is CMN. Is this some sort of acronym? Best regards, Krzysztof
