Add ACTLR data table for SC7280 along with support for
same including SC7280 specific implementation operations.
Signed-off-by: Bibek Kumar Patro <quic_bibekkum@xxxxxxxxxxx>
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 58 +++++++++++++++++++++-
1 file changed, 57 insertions(+), 1 deletion(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index dc143b250704..a776c7906c76 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -31,6 +31,55 @@
#define PREFETCH_MODERATE (2 << PREFETCH_SHIFT)
#define PREFETCH_DEEP (3 << PREFETCH_SHIFT)
+static const struct actlr_config sc7280_apps_actlr_cfg[] = {
+ { 0x0800, 0x04e0, PREFETCH_DEFAULT | CMTLB },
+ { 0x0900, 0x0402, PREFETCH_SHALLOW | CPRE | CMTLB },
+ { 0x0901, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB },
+ { 0x0d01, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB },
+ { 0x1181, 0x0420, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x1182, 0x0420, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x1183, 0x0420, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x1184, 0x0420, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x1185, 0x0420, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x1186, 0x0420, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x1187, 0x0420, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x1188, 0x0420, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x1189, 0x0420, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x118b, 0x0420, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x118c, 0x0420, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x118d, 0x0420, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x118e, 0x0420, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x118f, 0x0420, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x2000, 0x0020, PREFETCH_DEFAULT | CMTLB },
+ { 0x2040, 0x0000, PREFETCH_DEFAULT | CMTLB },
+ { 0x2062, 0x0000, PREFETCH_DEFAULT | CMTLB },
+ { 0x2080, 0x0020, PREFETCH_DEFAULT | CMTLB },
+ { 0x20c0, 0x0020, PREFETCH_DEFAULT | CMTLB },
+ { 0x2100, 0x0020, PREFETCH_DEFAULT | CMTLB },
+ { 0x2140, 0x0000, PREFETCH_DEFAULT | CMTLB },
+ { 0x2180, 0x0020, PREFETCH_SHALLOW | CPRE | CMTLB },
+ { 0x2181, 0x0004, PREFETCH_SHALLOW | CPRE | CMTLB },
+ { 0x2183, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB },
+ { 0x2184, 0x0020, PREFETCH_SHALLOW | CPRE | CMTLB },
+ { 0x2187, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB },
+};
+
+static const struct actlr_config sc7280_gfx_actlr_cfg[] = {
+ { 0x0000, 0x07ff, PREFETCH_DEEP | CPRE | CMTLB },
+};
+
+static const struct actlr_variant sc7280_actlr[] = {
+ {
+ .io_start = 0x15000000,
+ .actlrcfg = sc7280_apps_actlr_cfg,
+ .num_actlrcfg = ARRAY_SIZE(sc7280_apps_actlr_cfg)
+ }, {
+ .io_start = 0x03da0000,
+ .actlrcfg = sc7280_gfx_actlr_cfg,
+ .num_actlrcfg = ARRAY_SIZE(sc7280_gfx_actlr_cfg)
+ },
+};
+
static const struct actlr_config sm8550_apps_actlr_cfg[] = {
{ 0x0800, 0x0020, PREFETCH_DEFAULT | CMTLB },
{ 0x1800, 0x00c0, PREFETCH_DEFAULT | CMTLB },
@@ -689,6 +738,13 @@ static const struct qcom_smmu_match_data sdm845_smmu_500_data = {
/* Also no debug configuration. */
};
+static const struct qcom_smmu_match_data sc7280_smmu_500_impl0_data = {
+ .impl = &qcom_smmu_500_impl,
+ .adreno_impl = &qcom_adreno_smmu_500_impl,
+ .cfg = &qcom_smmu_impl0_cfg,
+ .actlrvar = sc7280_actlr,
+ .num_smmu = ARRAY_SIZE(sc7280_actlr),
+};
static const struct qcom_smmu_match_data sm8550_smmu_500_impl0_data = {
.impl = &qcom_smmu_500_impl,
@@ -715,7 +771,7 @@ static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
{ .compatible = "qcom,qdu1000-smmu-500", .data = &qcom_smmu_500_impl0_data },
{ .compatible = "qcom,sc7180-smmu-500", .data = &qcom_smmu_500_impl0_data },
{ .compatible = "qcom,sc7180-smmu-v2", .data = &qcom_smmu_v2_data },
- { .compatible = "qcom,sc7280-smmu-500", .data = &qcom_smmu_500_impl0_data },
+ { .compatible = "qcom,sc7280-smmu-500", .data = &sc7280_smmu_500_impl0_data },
{ .compatible = "qcom,sc8180x-smmu-500", .data = &qcom_smmu_500_impl0_data },
{ .compatible = "qcom,sc8280xp-smmu-500", .data = &qcom_smmu_500_impl0_data },
{ .compatible = "qcom,sdm630-smmu-v2", .data = &qcom_smmu_v2_data },
--
2.34.1
