On Wed, Jul 3, 2024 at 3:54 AM Connor Abbott <cwabbott0@xxxxxxxxx> wrote: > > After testing, there are more parameters that we're programming which > affect how UBWC tiles are laid out in memory and therefore affect > the Mesa implementation of VK_EXT_host_image_copy [1], which includes a > CPU implementation of tiling and detiling images. In particular we have: > > 1. ubwc_mode, which is used to enable level 1 bank swizzling to go back > to UBWC 1.0 when the implementation supports UBWC 2.0. a610 sets > this. > 2. macrotile_mode, which we previously left as default but according to > downstream we shouldn't for a680. > 3. level2_swizzling_dis, which according to downstream has to be set > differently for a663. > > I want as much as possible to avoid problems from people trying to > upstream Mesa/kernel support not knowing what they're doing and blindly > copying things, so let's make this very explicit that you must set the > correct parameters in the kernel and then make sure that Mesa always > gets the right parameters from the "source of truth" in the kernel by > adding two new UAPI parameters. The Mesa MR has already been updated to > use this if available. > > A secondary goal is to make the adreno settings look more like the MDSS > settings, by combining ubwc_mode and level2_swizzling_dis into a single > ubwc_swizzle parameter that matches the MDSS one. This will help with > creating a single source of truth for all drivers later. The UAPI also > matches this, and it makes the Mesa tiling and detiling implementation > simpler/more straightforward. > > For more information on what all these parameters mean, see the comments > I've added in the first commit and the giant comment in > src/freedreno/fdl/fd6_tiled_memcpy.c I've added in [1]. > > Testing of the Mesa MR both with and without this series is appreciated, > there are many different SoCs out there with different UBWC > configurations and I cannot test them all. > > [1] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26578 > > Signed-off-by: Connor Abbott <cwabbott0@xxxxxxxxx> for the series, Reviewed-by: Rob Clark <robdclark@xxxxxxxxx> But could you resend with updated a6xx.xml now that the perf cntrs have been corrected (to avoid further churn later) BR, -R > --- > Changes in v2: > - Move ubwc_config field descriptions to kerneldoc comments on the struct > - Link to v1: https://lore.kernel.org/r/20240702-msm-tiling-config-v1-0-adaa6a6e4523@xxxxxxxxx > > --- > Connor Abbott (3): > drm/msm: Update a6xx register XML > drm/msm: Expand UBWC config setting > drm/msm: Expose expanded UBWC config uapi > > drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 + > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 34 +- > drivers/gpu/drm/msm/adreno/adreno_gpu.c | 6 + > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 32 +- > drivers/gpu/drm/msm/registers/adreno/a6xx.xml | 1617 ++++++++++++++++++++++++- > include/uapi/drm/msm_drm.h | 2 + > 6 files changed, 1664 insertions(+), 31 deletions(-) > --- > base-commit: 269b88cb92e62e52718cd44c07b7517265193157 > change-id: 20240701-msm-tiling-config-c5f222f5db1c > > Best regards, > -- > Connor Abbott <cwabbott0@xxxxxxxxx> >
