Re: [PATCH v13 4/6] iommu/arm-smmu: add ACTLR data and support for SM8550

Bibek Kumar Patro <quic_bibekkum@xxxxxxxxxxx> · Wed, 10 Jul 2024 23:14:27 +0530

On 7/4/2024 4:53 PM, Dmitry Baryshkov wrote:
On Wed, 3 Jul 2024 at 15:15, Bibek Kumar Patro
<quic_bibekkum@xxxxxxxxxxx> wrote:



On 7/2/2024 12:04 AM, Dmitry Baryshkov wrote:
On Fri, Jun 28, 2024 at 07:34:33PM GMT, Bibek Kumar Patro wrote:
Add ACTLR data table for SM8550 along with support for
same including SM8550 specific implementation operations.

Signed-off-by: Bibek Kumar Patro <quic_bibekkum@xxxxxxxxxxx>
---
   drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 89 ++++++++++++++++++++++
   1 file changed, 89 insertions(+)

diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index 77c9abffe07d..b4521471ffe9 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -23,6 +23,85 @@

   #define CPRE                       (1 << 1)
   #define CMTLB                      (1 << 0)
+#define PREFETCH_SHIFT              8
+#define PREFETCH_DEFAULT    0
+#define PREFETCH_SHALLOW    (1 << PREFETCH_SHIFT)
+#define PREFETCH_MODERATE   (2 << PREFETCH_SHIFT)
+#define PREFETCH_DEEP               (3 << PREFETCH_SHIFT)
+
+static const struct actlr_config sm8550_apps_actlr_cfg[] = {
+    { 0x18a0, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB },
+    { 0x18e0, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB },
+    { 0x0800, 0x0020, PREFETCH_DEFAULT | CMTLB },
+    { 0x1800, 0x00c0, PREFETCH_DEFAULT | CMTLB },
+    { 0x1820, 0x0000, PREFETCH_DEFAULT | CMTLB },
+    { 0x1860, 0x0000, PREFETCH_DEFAULT | CMTLB },
+    { 0x0c01, 0x0020, PREFETCH_DEEP | CPRE | CMTLB },

- Please keep the list sorted

Sure Dmitry, will sort this list in reverse-christmas-tree order
in next iteration. Thanks for this input.

Why? Just sort basing on SID.


Apologies for delayed response.
It's initially sorted based on SID only, but as I see few of them are
not which you're pointing to.
I will check the table again and sort the SIDs which are left unsorted.


- Please comment, which devices use these settings.

As discussed in earlier versions of this patch, these table entries
are kind of just blind values for SMMU device, where SMMU do not have
idea on which SID belong to which client. During probe time when the
clients' Stream-ID has corresponding ACTLR entry then the driver would
set value in register.
Also some might have their prefetch settings as proprietary.
Hence did not add the comments for device using these settings.

Please mention devices that are going to use the SIDs.


Interested to know if there's a compelling reason to mention the device
name.
From SMMU driver perspective there's not much value proposition by
mentioning the names of devices using the SIDs.
Also sometimes it would be possible that the the SID value might change
a bit for each client from hardware perspective which would need to be
updated back in the driver <kind of an additional overhead for SMMU
driver>.
Hence I was in favour to avoid mentioning the name of devices, not
making it look like a placeholder for SIDs and corresponding ACTLR
values.
Please let me know if you still feel otherwise.

Thanks & regards,
Bibek


Thanks & regards,
Bibek


+    { 0x0c02, 0x0020, PREFETCH_DEEP | CPRE | CMTLB },
+    { 0x0c03, 0x0020, PREFETCH_DEEP | CPRE | CMTLB },
+    { 0x0c04, 0x0020, PREFETCH_DEEP | CPRE | CMTLB },
+    { 0x0c05, 0x0020, PREFETCH_DEEP | CPRE | CMTLB },
+    { 0x0c06, 0x0020, PREFETCH_DEEP | CPRE | CMTLB },
+    { 0x0c07, 0x0020, PREFETCH_DEEP | CPRE | CMTLB },
+    { 0x0c08, 0x0020, PREFETCH_DEEP | CPRE | CMTLB },
+    { 0x0c09, 0x0020, PREFETCH_DEEP | CPRE | CMTLB },
+    { 0x0c0c, 0x0020, PREFETCH_DEEP | CPRE | CMTLB },
+    { 0x0c0d, 0x0020, PREFETCH_DEEP | CPRE | CMTLB },
+    { 0x0c0e, 0x0020, PREFETCH_DEEP | CPRE | CMTLB },
+    { 0x0c0f, 0x0020, PREFETCH_DEEP | CPRE | CMTLB },
+    { 0x1961, 0x0000, PREFETCH_DEEP | CPRE | CMTLB },
+    { 0x1962, 0x0000, PREFETCH_DEEP | CPRE | CMTLB },
+    { 0x1963, 0x0000, PREFETCH_DEEP | CPRE | CMTLB },
+    { 0x1964, 0x0000, PREFETCH_DEEP | CPRE | CMTLB },
+    { 0x1965, 0x0000, PREFETCH_DEEP | CPRE | CMTLB },
+    { 0x1966, 0x0000, PREFETCH_DEEP | CPRE | CMTLB },
+    { 0x1967, 0x0000, PREFETCH_DEEP | CPRE | CMTLB },
+    { 0x1968, 0x0000, PREFETCH_DEEP | CPRE | CMTLB },
+    { 0x1969, 0x0000, PREFETCH_DEEP | CPRE | CMTLB },
+    { 0x196c, 0x0000, PREFETCH_DEEP | CPRE | CMTLB },
+    { 0x196d, 0x0000, PREFETCH_DEEP | CPRE | CMTLB },
+    { 0x196e, 0x0000, PREFETCH_DEEP | CPRE | CMTLB },
+    { 0x196f, 0x0000, PREFETCH_DEEP | CPRE | CMTLB },
+    { 0x19c1, 0x0010, PREFETCH_DEEP | CPRE | CMTLB },
+    { 0x19c2, 0x0010, PREFETCH_DEEP | CPRE | CMTLB },
+    { 0x19c3, 0x0010, PREFETCH_DEEP | CPRE | CMTLB },
+    { 0x19c4, 0x0010, PREFETCH_DEEP | CPRE | CMTLB },
+    { 0x19c5, 0x0010, PREFETCH_DEEP | CPRE | CMTLB },
+    { 0x19c6, 0x0010, PREFETCH_DEEP | CPRE | CMTLB },
+    { 0x19c7, 0x0010, PREFETCH_DEEP | CPRE | CMTLB },
+    { 0x19c8, 0x0010, PREFETCH_DEEP | CPRE | CMTLB },
+    { 0x19c9, 0x0010, PREFETCH_DEEP | CPRE | CMTLB },
+    { 0x19cc, 0x0010, PREFETCH_DEEP | CPRE | CMTLB },
+    { 0x19cd, 0x0010, PREFETCH_DEEP | CPRE | CMTLB },
+    { 0x19ce, 0x0010, PREFETCH_DEEP | CPRE | CMTLB },
+    { 0x19cf, 0x0010, PREFETCH_DEEP | CPRE | CMTLB },
+    { 0x1c00, 0x0002, PREFETCH_SHALLOW | CPRE | CMTLB },
+    { 0x1c01, 0x0000, PREFETCH_DEFAULT | CMTLB },
+    { 0x1920, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB },
+    { 0x1923, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB },
+    { 0x1924, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB },
+    { 0x1940, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB },
+    { 0x1941, 0x0004, PREFETCH_SHALLOW | CPRE | CMTLB },
+    { 0x1943, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB },
+    { 0x1944, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB },
+    { 0x1947, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB },
+};
+
+static const struct actlr_config sm8550_gfx_actlr_cfg[] = {
+    { 0x0000, 0x03ff, PREFETCH_DEEP | CPRE | CMTLB },
+};
+
+static const struct actlr_variant sm8550_actlr[] = {
+    {
+            .io_start = 0x15000000,
+            .actlrcfg = sm8550_apps_actlr_cfg,
+            .num_actlrcfg = ARRAY_SIZE(sm8550_apps_actlr_cfg)
+    }, {
+            .io_start = 0x03da0000,
+            .actlrcfg = sm8550_gfx_actlr_cfg,
+            .num_actlrcfg = ARRAY_SIZE(sm8550_gfx_actlr_cfg)
+    },
+};

   static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu)
   {
@@ -606,6 +685,15 @@ static const struct qcom_smmu_match_data sdm845_smmu_500_data = {
      /* Also no debug configuration. */
   };

+
+static const struct qcom_smmu_match_data sm8550_smmu_500_impl0_data = {
+    .impl = &qcom_smmu_500_impl,
+    .adreno_impl = &qcom_adreno_smmu_500_impl,
+    .cfg = &qcom_smmu_impl0_cfg,
+    .actlrvar = sm8550_actlr,
+    .num_smmu = ARRAY_SIZE(sm8550_actlr),
+};
+
   static const struct qcom_smmu_match_data qcom_smmu_500_impl0_data = {
      .impl = &qcom_smmu_500_impl,
      .adreno_impl = &qcom_adreno_smmu_500_impl,
@@ -640,6 +728,7 @@ static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
      { .compatible = "qcom,sm8250-smmu-500", .data = &qcom_smmu_500_impl0_data },
      { .compatible = "qcom,sm8350-smmu-500", .data = &qcom_smmu_500_impl0_data },
      { .compatible = "qcom,sm8450-smmu-500", .data = &qcom_smmu_500_impl0_data },
+    { .compatible = "qcom,sm8550-smmu-500", .data = &sm8550_smmu_500_impl0_data },
      { .compatible = "qcom,smmu-500", .data = &qcom_smmu_500_impl0_data },
      { }
   };
--
2.34.1





--
With best wishes
Dmitry







