On Tue, Apr 30, 2024 at 11:07:59PM GMT, Alexandru Gagniuc wrote:
> On ipq9574, there are 4 PCIe controllers. Describe the pcie2 and pcie3
> nodes, and their PHYs in devicetree.
>
> The pcie0 and pcie1 controllers use a gen3x1 PHY, which is not
> currently supported. Hence, only pcie2 and pcie3 are described. Only
> pcie2 was tested because my devboard only has conenctions to pcie2.
>
> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@xxxxxxxxx>
Seems the clock and phy got merged, but I don't see any feedback on the
PCI patches - and according to the msg-id there's 18 patches in the
series.
Please rebase on linux-next and submit v5, so we get clarity in what
remains to be merged.
Thanks,
Bjorn
> ---
> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 178 +++++++++++++++++++++++++-
> 1 file changed, 176 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> index 7f2e5cbf3bbb..c391886cf9ab 100644
> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> @@ -300,8 +300,8 @@ gcc: clock-controller@1800000 {
> <0>,
> <0>,
> <0>,
> - <0>,
> - <0>,
> + <&pcie2_phy>,
> + <&pcie3_phy>,
> <0>;
> #clock-cells = <1>;
> #reset-cells = <1>;
> @@ -745,6 +745,180 @@ frame@b128000 {
> status = "disabled";
> };
> };
> +
> + pcie2_phy: phy@8c000 {
> + compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy";
> + reg = <0x0008c000 0x14f4>;
> +
> + clocks = <&gcc GCC_PCIE2_AUX_CLK>,
> + <&gcc GCC_PCIE2_AHB_CLK>,
> + <&gcc GCC_PCIE2_PIPE_CLK>;
> + clock-names = "aux",
> + "cfg_ahb",
> + "pipe";
> +
> + clock-output-names = "pcie_phy2_pipe_clk";
> + #clock-cells = <0>;
> + #phy-cells = <0>;
> +
> + resets = <&gcc GCC_PCIE2_PHY_BCR>,
> + <&gcc GCC_PCIE2PHY_PHY_BCR>;
> + reset-names = "phy",
> + "common";
> + status = "disabled";
> + };
> +
> + pcie3_phy: phy@f4000 {
> + compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy";
> + reg = <0x000f4000 0x14f4>;
> +
> + clocks = <&gcc GCC_PCIE3_AUX_CLK>,
> + <&gcc GCC_PCIE3_AHB_CLK>,
> + <&gcc GCC_PCIE3_PIPE_CLK>;
> + clock-names = "aux",
> + "cfg_ahb",
> + "pipe";
> +
> + clock-output-names = "pcie_phy3_pipe_clk";
> + #clock-cells = <0>;
> + #phy-cells = <0>;
> +
> + resets = <&gcc GCC_PCIE3_PHY_BCR>,
> + <&gcc GCC_PCIE3PHY_PHY_BCR>;
> + reset-names = "phy",
> + "common";
> + status = "disabled";
> + };
> +
> + /* TODO: Populate pcie0/pcie1 when gen3x1 phy support is added. */
> +
> + pcie2: pcie@20000000 {
> + compatible = "qcom,pcie-ipq9574";
> + reg = <0x20000000 0xf1d>,
> + <0x20000f20 0xa8>,
> + <0x20001000 0x1000>,
> + <0x00088000 0x4000>,
> + <0x20100000 0x1000>;
> + reg-names = "dbi", "elbi", "atu", "parf", "config";
> +
> + ranges = <0x81000000 0x0 0x20200000 0x20200000 0x0 0x00100000>,
> + <0x82000000 0x0 0x20300000 0x20300000 0x0 0x07d00000>;
> +
> + device_type = "pci";
> + linux,pci-domain = <3>;
> + bus-range = <0x00 0xff>;
> + num-lanes = <2>;
> + max-link-speed = <3>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> +
> + phys = <&pcie2_phy>;
> + phy-names = "pciephy";
> +
> + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "msi";
> +
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0x7>;
> + interrupt-map = <0 0 0 1 &intc 0 0 164 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 2 &intc 0 0 165 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 3 &intc 0 0 186 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 4 &intc 0 0 187 IRQ_TYPE_LEVEL_HIGH>;
> +
> + clocks = <&gcc GCC_PCIE2_AXI_M_CLK>,
> + <&gcc GCC_PCIE2_AXI_S_CLK>,
> + <&gcc GCC_PCIE2_AXI_S_BRIDGE_CLK>,
> + <&gcc GCC_ANOC_PCIE2_2LANE_M_CLK>,
> + <&gcc GCC_SNOC_PCIE2_2LANE_S_CLK>,
> + <&gcc GCC_PCIE2_RCHNG_CLK>;
> + clock-names = "axi_m",
> + "axi_s",
> + "axi_bridge",
> + "rchng";
> +
> + resets = <&gcc GCC_PCIE2_PIPE_ARES>,
> + <&gcc GCC_PCIE2_AUX_ARES>,
> + <&gcc GCC_PCIE2_CORE_STICKY_ARES>,
> + <&gcc GCC_PCIE2_AXI_M_ARES>,
> + <&gcc GCC_PCIE2_AXI_S_ARES>,
> + <&gcc GCC_PCIE2_AXI_S_STICKY_ARES>,
> + <&gcc GCC_PCIE2_AXI_M_STICKY_ARES>,
> + <&gcc GCC_PCIE2_AHB_ARES>;
> + reset-names = "pipe",
> + "aux",
> + "sticky",
> + "axi_m",
> + "axi_s",
> + "axi_s_sticky",
> + "axi_m_sticky",
> + "ahb";
> + status = "disabled";
> + };
> +
> + pcie3: pcie@18000000 {
> + compatible = "qcom,pcie-ipq9574";
> + reg = <0x18000000 0xf1d>,
> + <0x18000f20 0xa8>,
> + <0x18001000 0x1000>,
> + <0x000f0000 0x4000>,
> + <0x18100000 0x1000>;
> + reg-names = "dbi", "elbi", "atu", "parf", "config";
> +
> + ranges = <0x81000000 0x0 0x18200000 0x18200000 0x0 0x00100000>,
> + <0x82000000 0x0 0x18300000 0x18300000 0x0 0x07d00000>;
> +
> + device_type = "pci";
> + linux,pci-domain = <4>;
> + bus-range = <0x00 0xff>;
> + num-lanes = <2>;
> + max-link-speed = <3>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> +
> + phys = <&pcie3_phy>;
> + phy-names = "pciephy";
> +
> + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "msi";
> +
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0x7>;
> + interrupt-map = <0 0 0 1 &intc 0 0 189 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 2 &intc 0 0 190 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 3 &intc 0 0 192 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 4 &intc 0 0 192 IRQ_TYPE_LEVEL_HIGH>;
> +
> + clocks = <&gcc GCC_PCIE3_AXI_M_CLK>,
> + <&gcc GCC_PCIE3_AXI_S_CLK>,
> + <&gcc GCC_PCIE3_AXI_S_BRIDGE_CLK>,
> + <&gcc GCC_ANOC_PCIE3_2LANE_M_CLK>,
> + <&gcc GCC_SNOC_PCIE3_2LANE_S_CLK>,
> + <&gcc GCC_PCIE3_RCHNG_CLK>;
> + clock-names = "axi_m",
> + "axi_s",
> + "axi_bridge",
> + "anoc",
> + "snoc",
> + "rchng";
> +
> + resets = <&gcc GCC_PCIE3_PIPE_ARES>,
> + <&gcc GCC_PCIE3_AUX_ARES>,
> + <&gcc GCC_PCIE3_CORE_STICKY_ARES>,
> + <&gcc GCC_PCIE3_AXI_M_ARES>,
> + <&gcc GCC_PCIE3_AXI_S_ARES>,
> + <&gcc GCC_PCIE3_AXI_S_STICKY_ARES>,
> + <&gcc GCC_PCIE3_AXI_M_STICKY_ARES>,
> + <&gcc GCC_PCIE3_AHB_ARES>;
> + reset-names = "pipe",
> + "aux",
> + "sticky",
> + "axi_m",
> + "axi_s",
> + "axi_s_sticky",
> + "axi_m_sticky",
> + "ahb";
> + status = "disabled";
> + };
> };
>
> thermal-zones {
> --
> 2.40.1
>
