Since those clocks are using rcg2_shared_ops to park on TCXO
instead of disable, no need to have TCXO in the frequency table.
Fixes: 9e939f008338 ("clk: qcom: add the SM8650 Display Clock Controller driver")
Signed-off-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx>
---
drivers/clk/qcom/dispcc-sm8650.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/clk/qcom/dispcc-sm8650.c b/drivers/clk/qcom/dispcc-sm8650.c
index 70944b7128e2..d22f61772667 100644
--- a/drivers/clk/qcom/dispcc-sm8650.c
+++ b/drivers/clk/qcom/dispcc-sm8650.c
@@ -272,7 +272,6 @@ static const struct clk_parent_data disp_cc_parent_data_9[] = {
};
static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
- F(19200000, P_BI_TCXO, 1, 0, 0),
F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0),
F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0),
{ }
@@ -580,7 +579,6 @@ static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = {
};
static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
- F(19200000, P_BI_TCXO, 1, 0, 0),
F(85714286, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
F(100000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
F(150000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
--
2.34.1
