While trying to fix a crash when display is started late in the
boot process, I ran on multiple issues with the DISPCC clock
definitions that needed some fixups.
Signed-off-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx>
---
Neil Armstrong (5):
clk: qcom: dispcc-sm8650: Park RCG's clk source at XO during disable
clk: qcom: dispcc-sm8650: use correct clk ops for dptx1_aux_clk_src
clk: qcom: dispcc-sm8650: drop TCXO from table when using rcg2_shared_ops
clk: qcom: dispcc-sm8650: add missing CLK_SET_RATE_PARENT flag
clk: qcom: dispcc-sm8650: Update the GDSC wait_val fields and flags
drivers/clk/qcom/dispcc-sm8650.c | 32 +++++++++++++++++++-------------
1 file changed, 19 insertions(+), 13 deletions(-)
---
base-commit: b992b79ca8bc336fa8e2c80990b5af80ed8f36fd
change-id: 20240621-topic-sm8650-upstream-fix-dispcc-a1994038c003
Best regards,
--
Neil Armstrong <neil.armstrong@xxxxxxxxxx>
