On Mon, Jun 03, 2024 at 04:57:15PM +0530, Sneh Shah wrote: > On 5/30/2024 1:39 AM, Russell King (Oracle) wrote: > > From what you're saying: > > - if using the dwmac1000 core, then for the registers at GMAC_PCS_BASE > > (0xc0 offset)... > > - if using the dwmac4 core, then for registers at GMAC_PCS_BASE > > (0xe0 offset)... > > ... is it true that only the GMAC_AN_CTRL() register is implemented > > and none of the other registers listed in stmmac_pcs.h? > > > > In terms of interrupts when the link status changes, how do they > > present? Are they through the GMAC_INT_RGSMIIS interrupt only? > > What about GMAC_INT_PCS_LINK or GMAC_INT_PCS_ANE? Or in the case > > of the other core, is it through the PCS_RGSMIIIS_IRQ interrupt > > only? Similarly, what about PCS_LINK_IRQ or PCS_ANE_IRQ? > > we only have GMAC_AN_CTRL and GMAC_AN_STATUS register. > There is no separate IRQ line for PCS link or autoneg. > It is notified via MAC interrupt line only.
