On 5/30/2024 1:39 AM, Russell King (Oracle) wrote: > On Wed, May 29, 2024 at 07:43:15PM +0530, Sneh Shah wrote: >> In this version of qualcomm ethernet, PCS is not an independent HW >> block. It is integrated to MAC block itself. It has very limited >> configuration.Here PCS doesn't have it's own link speed/duplex >> capabities. Hence we are bypassing all this PCS related functionalities. > > I want to concentrate on this part first - we'll address the 2.5G > issues separately once I've got a picture of this hardware (and thus > can work out what needs to change in my phylink_pcs implementation to > support the standard Cisco SGMII speeds. > > From what I understand you're saying, your integrated PCS is different > from the DesignWare integrated PCS? It's an inbuilt PCS block within designware ETHQoS core. > > Which core does it use? dwmac4_core.c or dwmac1000_core.c, or some > other? Not knowing which core makes asking the following questions > harder, since I'm having to double them up to cover both cores with > their different definitions. it is dwmac4 core with 0xe0 offset. > > Does it only present its status via the GMAC_PHYIF_CONTROL_STATUS or > GMAC_RGSMIIIS register? It is present via GMAC_PHYIF_CONTROL_STATUS. > > From what you're saying: > - if using the dwmac1000 core, then for the registers at GMAC_PCS_BASE > (0xc0 offset)... > - if using the dwmac4 core, then for registers at GMAC_PCS_BASE > (0xe0 offset)... > ... is it true that only the GMAC_AN_CTRL() register is implemented > and none of the other registers listed in stmmac_pcs.h? > > In terms of interrupts when the link status changes, how do they > present? Are they through the GMAC_INT_RGSMIIS interrupt only? > What about GMAC_INT_PCS_LINK or GMAC_INT_PCS_ANE? Or in the case > of the other core, is it through the PCS_RGSMIIIS_IRQ interrupt > only? Similarly, what about PCS_LINK_IRQ or PCS_ANE_IRQ? we only have GMAC_AN_CTRL and GMAC_AN_STATUS register. There is no separate IRQ line for PCS link or autoneg. It is notified via MAC interrupt line only. > > Thanks. >
