On Mon, May 27, 2024 at 10:20:36AM +0300, Abel Vesa wrote:
> The new X1E80100 SoC bumps up the HW version of QMP phy to v6 N4 for
> combo USB and DP PHY. Currently, the X1E80100 uses the pure V6 PCS
> register offsets, which are different. Add the offsets so the
> mentioned platform can be fixed later on. Add the new PCS offsets
> in a dedicated header file.
>
> Fixes: d7b3579f84f7 ("phy: qcom-qmp-combo: Add x1e80100 USB/DP combo phys")
> Co-developed-by: Kuogee Hsieh <quic_khsieh@xxxxxxxxxxx>
> Signed-off-by: Kuogee Hsieh <quic_khsieh@xxxxxxxxxxx>
> Signed-off-by: Abel Vesa <abel.vesa@xxxxxxxxxx>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6-n4.h | 32 +++++++++++++++++++++++++++
> 1 file changed, 32 insertions(+)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
--
With best wishes
Dmitry
