On Thu, 02 May 2024 10:00:35 +0200, Neil Armstrong wrote:
> The PCIe Gen4x2 PHY found in the SM8[456]50 SoCs have a second clock named
> "PHY_AUX_CLK" which is an input of the Global Clock Controller (GCC) which
> is muxed & gated then returned to the PHY as an input.
>
> Document the clock IDs to select the PIPE clock or the AUX clock,
> also enforce a second clock-output-names and a #clock-cells value of 1
> for the PCIe Gen4x2 PHY found in the SM8[456]50 SoCs.
>
> [...]
Applied, thanks!
[1/3] arm64: dts: qcom: sm8450: correct pcie1 phy clocks inputs to gcc
commit: e7686284066073e3f39b02df0f71db96d7538f48
[2/3] arm64: dts: qcom: sm8550: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk
commit: 0cc97d9e3fdf9a7b71b4edfd020a44c54c40df52
[3/3] arm64: dts: qcom: sm8650: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk
commit: d00b42f170dfa4d5ffbd616aec36de8159168bba
Best regards,
--
Bjorn Andersson <andersson@xxxxxxxxxx>
