The PCIe Gen4x2 PHY found in the SM8[456]50 SoCs have a second clock named "PHY_AUX_CLK" which is an input of the Global Clock Controller (GCC) which is muxed & gated then returned to the PHY as an input. Document the clock IDs to select the PIPE clock or the AUX clock, also enforce a second clock-output-names and a #clock-cells value of 1 for the PCIe Gen4x2 PHY found in the SM8[456]50 SoCs. The PHY driver needs a light refactoring to support a second clock, and finally the DT is changed to connect the PHY second clock to the corresponding GCC input then drop the dummy fixed rate clock. To: Bjorn Andersson <andersson@xxxxxxxxxx> To: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx> To: Rob Herring <robh@xxxxxxxxxx> To: Krzysztof Kozlowski <krzysztof.kozlowski+dt@xxxxxxxxxx> To: Conor Dooley <conor+dt@xxxxxxxxxx> Cc: linux-arm-msm@xxxxxxxxxxxxxxx Cc: devicetree@xxxxxxxxxxxxxxx Cc: linux-kernel@xxxxxxxxxxxxxxx Signed-off-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx> Changes in v5: - Reworked commit message to include more reasoning and details about the changes - Link to v4: https://lore.kernel.org/r/20240422-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v4-0-868b15a17a45@xxxxxxxxxx Changes in v4: - Fixed dtbs check error on sm8550-qrd.dtb after rebase on -next - Link to v3: https://lore.kernel.org/r/20240422-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v3-0-799475a27cce@xxxxxxxxxx Changes in v3: - Rebased on linux-next, applies now cleanly - Link to v2: https://lore.kernel.org/r/20240322-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v2-0-3ec0a966d52f@xxxxxxxxxx Changes in v2: - Collected review tags - Switched back to of_clk_add_hw_provider/devm_add_action_or_reset to maintain compatibility - Tried to use generic of_clk_hw_onecell_get() but it requires to much boilerplate code and would still need a local qmp_pcie_clk_hw_get() to support the current #clock-cells=0 when exposing 2 clocks, so it's simpler to just return the clocks in qmp_pcie_clk_hw_get() - Link to v1: https://lore.kernel.org/r/20240319-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v1-0-926d7a4ccd80@xxxxxxxxxx --- Neil Armstrong (3): arm64: dts: qcom: sm8450: correct pcie1 phy clocks inputs to gcc arm64: dts: qcom: sm8550: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk arm64: dts: qcom: sm8650: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk arch/arm64/boot/dts/qcom/sm8450.dtsi | 8 ++++---- arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 4 ---- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 4 ---- arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 19 ------------------- arch/arm64/boot/dts/qcom/sm8550.dtsi | 13 ++++--------- arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 4 ---- arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 4 ---- arch/arm64/boot/dts/qcom/sm8650.dtsi | 13 ++++--------- 8 files changed, 12 insertions(+), 57 deletions(-) --- base-commit: 1d0a6cdb7d77a14da03246bb6f10a489ad49af41 change-id: 20240319-topic-sm8x50-upstream-pcie-1-phy-aux-clk-4b35169707dd Best regards, -- Neil Armstrong <neil.armstrong@xxxxxxxxxx>
