On 5/3/2024 3:38 AM, Stephen Boyd wrote:
Quoting Md Sadre Alam (2024-05-01 20:42:47)
Add BRANCH_HALT_VOTED flag to inform clock framework
don't check for CLK_OFF bit.
CRYPTO_AHB_CLK_ENA and CRYPTO_AXI_CLK_ENA enable bit is
present in other VOTE registers also, like TZ.
If anyone else also enabled this clock, even if we turn
off in GCC_APCS_CLOCK_BRANCH_ENA_VOTE | 0x180B004, it won't
turn off.
Are you seeing problems where we need to send this patch to stable?
Yes
Signed-off-by: Md Sadre Alam <quic_mdalam@xxxxxxxxxxx>
---
Any fixes tag?
Will add in next patch
drivers/clk/qcom/gcc-ipq9574.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
index 0a3f846695b8..f8b9a1e93bef 100644
--- a/drivers/clk/qcom/gcc-ipq9574.c
+++ b/drivers/clk/qcom/gcc-ipq9574.c
@@ -2140,9 +2140,10 @@ static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
static struct clk_branch gcc_crypto_axi_clk = {
.halt_reg = 0x16010,
+ .halt_check = BRANCH_HALT_VOTED,
.clkr = {
- .enable_reg = 0x16010,
- .enable_mask = BIT(0),
+ .enable_reg = 0xb004,
You could be more explicit in the commit text that you're changing the
register offset to the voting register.
will update the commit message in next patch.
+ .enable_mask = BIT(15),
Thanks for reviewing.
Regards,
Alam.
