On several Qualcomm platforms DisplayPort link clocks used incorrect frequency tables. Drop frequency tables and use clk_byte2_ops instead of clk_rcg2_ops. Note, this was tested on SM8450 only and then extended to other platforms. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx> --- Changes in v2: - Expanded commit messages to mention exact issue being fixed and the triggering message (Stephen Boyd, Bjorn) - Link to v1: https://lore.kernel.org/r/20240408-dispcc-dp-clocks-v1-0-f9e44902c28d@xxxxxxxxxx --- Dmitry Baryshkov (4): clk: qcom: dispcc-sm8450: fix DisplayPort clocks clk: qcom: dispcc-sm6350: fix DisplayPort clocks clk: qcom: dispcc-sm8550: fix DisplayPort clocks clk: qcom: dispcc-sm8650: fix DisplayPort clocks drivers/clk/qcom/dispcc-sm6350.c | 11 +---------- drivers/clk/qcom/dispcc-sm8450.c | 20 ++++---------------- drivers/clk/qcom/dispcc-sm8550.c | 20 ++++---------------- drivers/clk/qcom/dispcc-sm8650.c | 20 ++++---------------- 4 files changed, 13 insertions(+), 58 deletions(-) --- base-commit: a59668a9397e7245b26e9be85d23f242ff757ae8 change-id: 20240408-dispcc-dp-clocks-5ee5d5926346 Best regards, -- Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
