On 4/19/24 02:09, Shashank Babu Chinta Venkata wrote:
GEN3_RELATED_OFFSET is being used to determine data rate of shadow registers. Select data rate as 16GT/s and set appropriate equilization settings to improve link stability for 16GT/s data rate. Signed-off-by: Shashank Babu Chinta Venkata <quic_schintav@xxxxxxxxxxx> ---
[...]
+ reg = dw_pcie_readl_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF); + reg = GEN3_EQ_FMDC_T_MIN_PHASE23(0) | + GEN3_EQ_FMDC_N_EVALS(0xD) | + GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA(0x5) | + GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA(0x5); + dw_pcie_writel_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF, reg); + + reg = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF); + reg = GEN3_EQ_CONTROL_OFF_FB_MODE(0) | + GEN3_EQ_CONTROL_OFF_PHASE23_EXIT_MODE(0) | + GEN3_EQ_CONTROL_OFF_FOM_INC_INITIAL_EVAL(0) | + GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC(0); + dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, reg);
Also, any chance we could get some explanations as to what these magic values mean? Preferably in the form of a #define for each one Konrad
