On 22/03/2024 11:58, Dmitry Baryshkov wrote:
The SuperSpeed signals originate from the DWC3 host controller and then are routed through the Combo QMP PHY, where they are multiplexed with the DisplayPort signals. Add corresponding OF graph link. Reported-by: Luca Weiss <luca.weiss@xxxxxxxxxxxxx> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx> --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index d57039a4c3aa..e551e733ab94 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -3917,6 +3917,10 @@ port@0 {port@1 {reg = <1>; + + usb_1_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_1_dwc3_ss_out>; + }; };port@2 {@@ -4195,8 +4199,24 @@ usb_1_dwc3: usb@a600000 { phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy";- port {- usb_1_dwc3_hs_out: endpoint {}; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_dwc3_hs_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_dwc3_ss_out: endpoint { + remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; + }; + }; }; }; };
I think these should go into platform definitions, there's nothing at the SoC level that imposes the port constraint.
--- bod
