On 19/03/2024 11:44, Neil Armstrong wrote: > The PCIe Gen4x2 PHY found in the SM8[456]50 SoCs have a second clock named > "PHY_AUX_CLK" which is an input of the Global Clock Controller (GCC) which > is muxed & gated then returned to the PHY as an input. > > Document the clock IDs to select the PIPE clock or the AUX clock, > also enforce a second clock-output-names and a #clock-cells value of 1 > for the PCIe Gen4x2 PHY found in the SM8[456]50 SoCs. > > Signed-off-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> Best regards, Krzysztof
