The PCIe Gen4x2 PHY found in the SM8[456]50 SoCs have a second clock named
"PHY_AUX_CLK" which is an input of the Global Clock Controller (GCC) which
is muxed & gated then returned to the PHY as an input.
Document the clock IDs to select the PIPE clock or the AUX clock,
also enforce a second clock-output-names and a #clock-cells value of 1
for the PCIe Gen4x2 PHY found in the SM8[456]50 SoCs.
The PHY driver needs a light refactoring to support a second clock,
and finally the DT is changed to connect the PHY second clock to the
corresponding GCC input then drop the dummy fixed rate clock.
Signed-off-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx>
---
Neil Armstrong (7):
dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: document PHY AUX clock on SM8[456]50 SoCs
phy: qcom: qmp-pcie: refactor clock register code
phy: qcom: qmp-pcie: register second optional PHY AUX clock
phy: qcom: qmp-pcie: register PHY AUX clock for SM8[456]50 4x2 PCIe PHY
arm64: dts: qcom: sm8450: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk
arm64: dts: qcom: sm8550: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk
arm64: dts: qcom: sm8650: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk
.../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 27 +++++-
arch/arm64/boot/dts/qcom/sm8450.dtsi | 8 +-
arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 4 -
arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 4 -
arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 8 --
arch/arm64/boot/dts/qcom/sm8550.dtsi | 13 +--
arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 4 -
arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 4 -
arch/arm64/boot/dts/qcom/sm8650.dtsi | 13 +--
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 104 ++++++++++++++++++---
include/dt-bindings/phy/phy-qcom-qmp.h | 4 +
11 files changed, 129 insertions(+), 64 deletions(-)
---
base-commit: 2e93f143ca010a5013528e1cfdc895f024fe8c21
change-id: 20240319-topic-sm8x50-upstream-pcie-1-phy-aux-clk-4b35169707dd
Best regards,
--
Neil Armstrong <neil.armstrong@xxxxxxxxxx>
