Re: [PATCH 4/7] phy: qcom: qmp-pcie: register PHY AUX clock for SM8[456]50 4x2 PCIe PHY

[Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>]

On Tue, 19 Mar 2024 at 12:46, Neil Armstrong <neil.armstrong@xxxxxxxxxx> wrote:
>
> The PCIe Gen4x2 PHY found in the SM8[456]50 SoCs have a second clock,
> enable this second clock by setting the proper 20MHz hardware rate in
> the Gen4x2 SM8[456]50 aux_clock_rate config fields.
>
> Signed-off-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx>
> ---
>  drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 9 +++++++++
>  1 file changed, 9 insertions(+)

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>

-- 
With best wishes
Dmitry