On 28/02/2024 14:07, Mrinmay Sarkar wrote: > > On 2/24/2024 3:49 PM, Krzysztof Kozlowski wrote: >> On 23/02/2024 15:03, Mrinmay Sarkar wrote: >>> Due to some hardware changes, SA8775P has set the NO_SNOOP attribute >>> in its TLP for all the PCIe controllers. NO_SNOOP attribute when set, >>> the requester is indicating that there no cache coherency issues exit >>> for the addressed memory on the host i.e., memory is not cached. But >>> in reality, requester cannot assume this unless there is a complete >>> control/visibility over the addressed memory on the host. >>> >>> And worst case, if the memory is cached on the host, it may lead to >>> memory corruption issues. It should be noted that the caching of memory >>> on the host is not solely dependent on the NO_SNOOP attribute in TLP. >>> >>> So to avoid the corruption, this patch overrides the NO_SNOOP attribute >>> by setting the PCIE_PARF_NO_SNOOP_OVERIDE register. This patch is not >>> needed for other upstream supported platforms since they do not set >>> NO_SNOOP attribute by default. >>> >>> This series is to enable cache snooping logic in both RC and EP driver >>> and add the "dma-coherent" property in dtsi to support cache coherency >>> in SA8775P platform. >> Please confirm that your patchset passes 100% dtbs_check. >> >> Best regards, >> Krzysztof > > I have run dtbs_check and it is passing. Hm, last time I checked dma-coherent was not allowed. Best regards, Krzysztof
