On Sun, 25 Feb 2024 at 19:34, Gabor Juhos <j4g8y7@xxxxxxxxx> wrote: > > The current register offset used for the GCC_UBI0_AXI_ARES reset > seems wrong. Or at least, the downstream driver uses [1] the same > offset which is used for other the GCC_UBI0_*_ARES resets. > > Change the code to use the same offset used in the downstream > driver and also specify the reset bit explicitly to use the > same format as the followup entries. > > 1. https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/blob/NHSS.QSDK.12.4.r4/drivers/clk/qcom/gcc-ipq5018.c?ref_type=heads#L3773 > > Fixes: e3fdbef1bab8 ("clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018") > Signed-off-by: Gabor Juhos <j4g8y7@xxxxxxxxx> > --- > drivers/clk/qcom/gcc-ipq5018.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx> -- With best wishes Dmitry
