On 21/02/2024 04:41, Manivannan Sadhasivam wrote:
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx> --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 01e4dfc4babd..e874cc4f8e6f 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1824,6 +1824,16 @@ pcie0: pcie@1c00000 { pinctrl-0 = <&pcie0_default_state>;status = "disabled";+ + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; };pcie0_phy: phy@1c06000 {@@ -1931,6 +1941,16 @@ pcie1: pcie@1c08000 { pinctrl-0 = <&pcie1_default_state>;status = "disabled";+ + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; };pcie1_phy: phy@1c0e000 {
Reviewed-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx>
