On 25.01.2024 17:55, Neil Armstrong wrote: > Both PCIe0 and PCIe1 controllers are capable of signalling the MSIs > received from endpoint devices to the CPU using GIC-ITS MSI controller. > Add support for it. > > The GIC-ITS MSI implementation provides an advantage over internal MSI > implementation using Locality-specific Peripheral Interrupts (LPI) that > would allow MSIs to be targeted for each CPU core. > > Like SM8450 & SM8550, the IDs are swapped, but works fine on PCIe0 and PCIe1. > > WiFi PCIe Device on SM8650-QRD using GIC-ITS: > 159: 0 0 0 0 0 0 0 0 ITS-MSI 0 Edge PCIe PME, aerdrv > 167: 0 4 0 0 0 0 0 0 ITS-MSI 524288 Edge bhi > 168: 0 0 4 0 0 0 0 0 ITS-MSI 524289 Edge mhi > 169: 0 0 0 34 0 0 0 0 ITS-MSI 524290 Edge mhi > 170: 0 0 0 0 3 0 0 0 ITS-MSI 524291 Edge ce0 > 171: 0 0 0 0 0 2 0 0 ITS-MSI 524292 Edge ce1 > 172: 0 0 0 0 0 0 806 0 ITS-MSI 524293 Edge ce2 > 173: 0 0 0 0 0 0 0 76 ITS-MSI 524294 Edge ce3 > 174: 0 0 0 0 0 0 0 0 ITS-MSI 524295 Edge ce5 > 175: 0 13 0 0 0 0 0 0 ITS-MSI 524296 Edge DP_EXT_IRQ > 176: 0 0 0 0 0 0 0 0 ITS-MSI 524297 Edge DP_EXT_IRQ Is it by chance that this one never fired? (lgtm otherwise) Konrad
